Matthew R. Wordeman

Generalized scaling theory and its application to a ¼ micrometer MOSFET design

In this paper we present a generalized scaling theory which allows for an independent scaling of the FET physical dimensions and applied voltages, while still maintaining constant the shape of the electric-field pattern. Thus two-dimensional effects are kept under control even though the intensity of the field is allowed to increase. The resulting design flexibility allows the design of FETs with quarter-micrometer channel length to be made, for either room temperature or liquid-nitrogen temperature. The physical limitations of the scaling theory are then investigated in detail, leading to the conclusion that the limiting FET performances are not reached at the 0.25-µm channel length. Further improvements are possible in the future, provided certain technology breakthroughs are achieved.

A new 'shift and ratio' method for MOSFET channel-length extraction

A shift-and-ratio method for extracting MOSFET channel length is presented. In this method, channel mobility can be any function of gate voltage, and high source-drain resistance does not affect extraction results. It is shown to yield more accurate and consistent channel lengths for deep-submicrometer CMOS devices at room and low temperatures. It is also found that, for both nFET and pFET, the source-drain resistance is essentially independent of temperature from 300 to 77 K.<<ETX>>

High transconductance and velocity overshoot in NMOS devices at the 0.1- mu m gate-length level

Transport properties are investigated in self-aligned NMOS devices with gate lengths down to 0.07 mu m. Velocity overshoot was observed in the form of the highest transconductances measured to date in Si FETs, as well as in the trend of the transconductance with gate length. The measured transconductance reached 910 mu S/ mu m at liquid-nitrogen temperature and 590 mu S/ mu m at room temperature. Velocity overshoot, by making such transconductances possible, should extend the value of miniaturization to dimensions that are smaller than what was commonly assumed to be worthwhile to pursue.<<ETX>>

Design and experimental technology for 0.1-&#181;m gate-length low-temperature operation FET's

The first device performance results are presented from experiments designed to assess FET technology feasibility in the 0.1-µm gate-length regime. Low-temperature device design considerations for these dimensions lead to a 0.15-V threshold and 0.6-V power supply, with a forward-biased substrate. Self-aligned and almost fully scaled devices and simple circuits were fabricated by direct-write electron-beam lithography at all levels, with gate lengths down to 0.07 µm. Measured device characteristics yielded over 750-mS/mm transconductance, which is the highest value obtained to date in Si FETs.

Wafer-level 3D integration technology

An overview of wafer-level three-dimensional (3D)) integration technology is provided. The basic reasoning for pursuing 3D integration is presented, followed by a description of the possible process variations and integration schemes, as well as the process technology elements needed to implement 3D integrated circuits. Detailed descriptions of two wafer-level integration schemes implemented at IBM are given, and the challenges of bringing 3D integration into a production environment are discussed.

A high-performance 0.25- mu m CMOS technology. II. Technology

For Pt. I, see ibid., vol.39, no.4, pp.959-966 (1992). The key technology elements and their integration into a high-performance, selectively scaled, 0.25- mu m CMOS technology are presented. Dual poly gates are fabricated using a process where the poly and source/drain (S/D) are doped simultaneously. The critical issues related to the dual poly gate are addressed. A reduced operating voltage of 2.5 V is used which allows the application of shallow junctions with abrupt profiles (no LDD) to minimize the device series resistance as well as gate to source/drain overlap capacitance. The poly gate and the S/D sheet resistances are lowered, using a thin salicide (TiSi/sub 2/) process. The TiSi/sub 2/ thickness is reduced to maintain low leakage and low contact resistance for the shallow S/D junctions. The gate level with 0.4- mu m physical length is defined using optical lithography with a contrast enhanced layer (CEL) resist system. >

A high-performance 0.25- mu m CMOS technology. I. Design and characterization

A high-performance 0.25- mu m-channel CMOS technology is designed and characterized. The technology utilizes n/sup +/ polysilicon gates on nFETs and p/sup +/ polysilicon gates on pFETs so that both FETs are surface channel devices. The gate oxide thickness is 7 nm. Abrupt As and B source/drain junctions with reduced power supply voltage are used to achieve high-speed operation. The technology yields a loaded ring oscillator (NAND, FI=FO=3, C/sub w/=0.2 pF) delay per stage of 280 ps at W/sub eff//L/sub eff/=15 mu m/0.25 mu m, which is a 1.7* improvement over 0.5- mu m CMOS technology. At a channel length of 0.18 mu m, a CMOS stage delay of 38 ps for unloaded inverter and 185 ps for loaded NAND ring oscillators were measured. Key design issues of the CMOS devices are discussed. >

On the accuracy of channel length characterization of LDD MOSFET's

A comprehensive investigation into the various mechanisms that limit the accuracy of channel length extraction techniques for lightly doped drain (LDD) MOSFETs is presented. Analytic equations are derived to quantify the sensitivity of the extraction techniques to the geometry effect, and bias dependence of the n-source and drain resistance. The analytic approach is supplemented and verified by exercising channel length extraction algorithms on current-voltage characteristics obtained from rigorous numerical simulations of a variety of LDD MOSFETs. The analyses clearly show that low gate overdrives and consistent threshold voltage measurements are required to accurately extract the metallurgical channel length. The analytic equations can be used to project the limitations of channel length extraction methods for future submicrometer LDD MOSFETs.

Alpha-particle-induced soft error rate in VLSI circuits

We study soft error rates (SER) in VLSI circuits, where the charge capable of causing a soft error becomes only a few percent of that created by a typical α-particle impacting on the circuits. Theoretical investigations are done considering a DRAM test vehicle, with the assumption that it is exposed to α-particles emanating from materials on the chip. We examine the effects of scaling on the SER and investigate the performance of several device structural modifications that can be introduced to decrease SER. We present experimental results on the achieved reduction in the charge that surface nodes collect when structural modifications are introduced. We find, both experimentally and theoretically, that the most promising modification is the incorporation of a buried grid of opposite conductivity type from the substrate. In general, however, as stored charge shrinks, multiple errors become prevalent, and SER reduction due to fabrication changes becomes less effective.

Fabrication of CMOS on ultrathin SOI obtained by epitaxial lateral overgrowth and chemical-mechanical polishing

A novel method for obtaining ultra-thin, defect-free silicon on insulator (SOI) film is introduced. This technique uses epitaxial lateral overgrowth of Si (ELO) and chemical-mechanical polishing (CMP). SOI films with thicknesses of 100 nm were obtained. These films were used in fabrication and dual poly CMOS devices. The quality of the SOI film obtained is the same as that of bulk silicon, and the device characteristics are comparable with those of devices fabricated on bulk. A minimum geometry unloaded inverter ring oscillator on SOI film obtained by ELO and CMP showed a speed improvement of 3* over the bulk devices.<<ETX>>