Bijan Davari

CMOS scaling for high performance and low power-the next ten years

A guideline for scaling of CMOS technology for logic applications such as microprocessors is presented covering the next ten years, assuming that the lithography and base process development driven by DRAM continues on the same three-year cycle as in the past. This paper emphasizes the importance of optimizing the choice of power-supply voltage. Two CMOS device and voltage scaling scenarios are described. One optimized for highest speed and the other trading off speed improvement for much lower power. It is shown that the low power scenario is quite close to the original constant electric-field scaling theory. CMOS technologies ranging from 0.25 /spl mu/m channel length at 2.5 V down to sub-0.1 /spl mu/m at 1 V are presented and power density is compared for the two scenarios. Scaling of the threshold voltage along with the power supply voltage will lead to a substantial rise in standby power compared to active power and some tradeoffs of performance and/or changes in design methods must be made. Key technology elements and their impact on scaling are discussed. It is shown that a speed improvement of about 7/spl times/ and over two orders of magnitude improvement in power-delay product (mW/MIPS) are expected by scaling of bulk CMOS down to the sub-0.1 /spl mu/m regime as compared with todays high performance 0.6 /spl mu/m devices at 5 V. However, the power density rises by a factor of 4/spl times/ for the high-speed scenario. The status of the silicon-on-insulator (SOI) approach to scaled CMOS is also reviewed, showing the potential for about 3/spl times/ savings in power compared to the bulk case at the same speed. >

A new 'shift and ratio' method for MOSFET channel-length extraction

A shift-and-ratio method for extracting MOSFET channel length is presented. In this method, channel mobility can be any function of gate voltage, and high source-drain resistance does not affect extraction results. It is shown to yield more accurate and consistent channel lengths for deep-submicrometer CMOS devices at room and low temperatures. It is also found that, for both nFET and pFET, the source-drain resistance is essentially independent of temperature from 300 to 77 K.<<ETX>>

A variable-size shallow trench isolation (STL) technology with diffused sidewall doping for submicron CMOS

A shallow trench isolation (STI) technology, RIE (reactive ion etching), CVD (chemical vapor deposition) oxide fill, and polarization are used to realize lithography-limited, submicron device and isolation dimensions. A novel boron diffusion technique is used for nMOSFET field doping, so that the parasitic sidewall inversion (leakage) problem is eliminated. It is shown that both the channel width bias and the narrow channel effect are greatly reduced in the STI technology. The diffused field also allows the boron doping to be self-aligned to the n-well with a single masking step in CMOS. STI is used in conjunction with a MINT (merged isolation and node trench) cell in 16-Mb DRAM (dynamic random access memory) technology.<<ETX>>

Workload and network-optimized computing systems

This paper describes a recent system-level trend toward the use of massive on-chip parallelism combined with efficient hardware accelerators and integrated networking to enable new classes of applications and computing-systems functionality. This system transition is driven by semiconductor physics and emerging network-application requirements. In contrast to general-purpose approaches, workload and network-optimized computing provides significant cost, performance, and power advantages relative to historical frequency-scaling approaches in a serial computational model. We highlight the advantages of on-chip network optimization that enables efficient computation and new services at the network edge of the data center. Software and application development challenges are presented, and a service-oriented architecture application example is shown that characterizes the power and performance advantages for these systems. We also discuss a roadmap for next-generation systems that proportionally scale with future networking bandwidth growth rates and employ 3-D chip integration methods for design flexibility and modularity.

A high-performance 0.25- mu m CMOS technology. II. Technology

For Pt. I, see ibid., vol.39, no.4, pp.959-966 (1992). The key technology elements and their integration into a high-performance, selectively scaled, 0.25- mu m CMOS technology are presented. Dual poly gates are fabricated using a process where the poly and source/drain (S/D) are doped simultaneously. The critical issues related to the dual poly gate are addressed. A reduced operating voltage of 2.5 V is used which allows the application of shallow junctions with abrupt profiles (no LDD) to minimize the device series resistance as well as gate to source/drain overlap capacitance. The poly gate and the S/D sheet resistances are lowered, using a thin salicide (TiSi/sub 2/) process. The TiSi/sub 2/ thickness is reduced to maintain low leakage and low contact resistance for the shallow S/D junctions. The gate level with 0.4- mu m physical length is defined using optical lithography with a contrast enhanced layer (CEL) resist system. >

A high-performance 0.25- mu m CMOS technology. I. Design and characterization

A high-performance 0.25- mu m-channel CMOS technology is designed and characterized. The technology utilizes n/sup +/ polysilicon gates on nFETs and p/sup +/ polysilicon gates on pFETs so that both FETs are surface channel devices. The gate oxide thickness is 7 nm. Abrupt As and B source/drain junctions with reduced power supply voltage are used to achieve high-speed operation. The technology yields a loaded ring oscillator (NAND, FI=FO=3, C/sub w/=0.2 pF) delay per stage of 280 ps at W/sub eff//L/sub eff/=15 mu m/0.25 mu m, which is a 1.7* improvement over 0.5- mu m CMOS technology. At a channel length of 0.18 mu m, a CMOS stage delay of 38 ps for unloaded inverter and 185 ps for loaded NAND ring oscillators were measured. Key design issues of the CMOS devices are discussed. >

A room temperature 0.1 /spl mu/m CMOS on SOI

An advanced 0.1 /spl mu/m CMOS technology on SOI is presented. In order to minimize short channel effects, relatively thick nondepleted (0.15 /spl mu/m) SOI film, highly nonuniform channel doping and source-drain extension-halo were used. Excellent short channel effects (SCE) down to channel lengths below 0.1 /spl mu/m were obtained. It is shown that undepleted SOI results in better short channel effect when compared to ultrathin depleted SOI. Devices with little short channel effect all the way to below 500 /spl Aring/ effective channel length were obtained. Furthermore, utilization of source-drain extension-halo minimizes the bipolar effect inherent in the floating body. These devices were applied to a variety of circuits: Very high speeds were obtained: Unloaded delay was 20 ps, unloaded NAND (FI=FO=3) was 64 ps, and loaded NAND (FI=FO=3, C/sub L/=0.3 pF) delay was 130 ps at supply of 1.8 V. This technology was applied to a self-resetting 512 K SRAM. Access times of 2.5 ns at 1.5 V and 3.5 ns at 1.0 V were obtained. >

Indium channel implant for improved short-channel behavior of submicrometer NMOSFETs

Indium has been used as an alternative channel implant in submicrometer-channel Si MOSFETs in order to obtain highly nonuniform channel doping. Superior device characteristics have been obtained down to 0.17- mu m channel length. The device characteristics have been compared to those of uniform boron-implanted short-channel MOSFETs used in a 0.25- mu m CMOS technology. Results indicate that NMOSFETs with nonuniform channel doping obtained with indium have superior short-channel effect (SCE) when compared to NMOSFETs with uniformly (boron) doped channel.<<ETX>>

Fabrication of CMOS on ultrathin SOI obtained by epitaxial lateral overgrowth and chemical-mechanical polishing

A novel method for obtaining ultra-thin, defect-free silicon on insulator (SOI) film is introduced. This technique uses epitaxial lateral overgrowth of Si (ELO) and chemical-mechanical polishing (CMP). SOI films with thicknesses of 100 nm were obtained. These films were used in fabrication and dual poly CMOS devices. The quality of the SOI film obtained is the same as that of bulk silicon, and the device characteristics are comparable with those of devices fabricated on bulk. A minimum geometry unloaded inverter ring oscillator on SOI film obtained by ELO and CMP showed a speed improvement of 3* over the bulk devices.<<ETX>>

A novel high-performance lateral bipolar on SOI

A novel lateral bipolar structure on SOI (silicon-on-insulator) is described. This device has a thin double-diffused base and a narrow emitter width, determined by the SOI thickness. It has minimal parasitic junction capacitance, as well as minimal emitter and collector resistances. Excellent device characteristics and an f/sub T/ of about 20 GHz were demonstrated.<<ETX>>