E. Ganin

High transconductance and velocity overshoot in NMOS devices at the 0.1- mu m gate-length level

Transport properties are investigated in self-aligned NMOS devices with gate lengths down to 0.07 mu m. Velocity overshoot was observed in the form of the highest transconductances measured to date in Si FETs, as well as in the trend of the transconductance with gate length. The measured transconductance reached 910 mu S/ mu m at liquid-nitrogen temperature and 590 mu S/ mu m at room temperature. Velocity overshoot, by making such transconductances possible, should extend the value of miniaturization to dimensions that are smaller than what was commonly assumed to be worthwhile to pursue.<<ETX>>

Design and experimental technology for 0.1-&#181;m gate-length low-temperature operation FET's

The first device performance results are presented from experiments designed to assess FET technology feasibility in the 0.1-µm gate-length regime. Low-temperature device design considerations for these dimensions lead to a 0.15-V threshold and 0.6-V power supply, with a forward-biased substrate. Self-aligned and almost fully scaled devices and simple circuits were fabricated by direct-write electron-beam lithography at all levels, with gate lengths down to 0.07 µm. Measured device characteristics yielded over 750-mS/mm transconductance, which is the highest value obtained to date in Si FETs.

Graded-SiGe-base, poly-emitter heterojunction bipolar transistors

Si/Si/sub 1-x/Ge/sub x/ heterojunction bipolar transistors (HBTs) fabricated using a low-temperature epitaxial technique to form the SiGe graded-bandgap base layer are discussed. These devices were fabricated on patterned substrates and subjected to annealing cycles used in advanced bipolar processing. These devices, which have base widths under 75 mm, were found to have excellent junction qualities. Due to the small bandgap of SiGe, the collector current at low bias is ten times higher than that for Si-base devices that have a pinched base resistance. This collector current ratio increases to more than 40 at LN/sub 2/ temperature resulting in current gains of 1600 for the SiGe-base transistors despite base sheet resistances as low as 7.5 k Omega / Square Operator .<<ETX>>

High-performance devices for a 0.15- mu m CMOS technology

Devices have been designed and fabricated in a CMOS technology with a nominal channel length of 0.15 mu m and minimum channel length below 0.1 mu m. In order to minimize short-channel effects (SCEs) down to channel lengths below 0.1 mu m, highly nonuniform channel dopings (obtained by indium and antimony channel implants) and shallow source-drain extensions/halo (by In and Sb preamorphization and low-energy As and BF/sub 2/ implant were used. Maximum high V/sub DS/ threshold rolloff was 250 mV at effective channel length of 0.06 mu m. For the minimum channel length of 0.1 mu m, the loaded (FI=FO=3, C=240 fF) and unloaded delays were 150 and 25 ps, respectively.<<ETX>>

Shallow p+ junction formation by a reverse‐type dopant preamorphization scheme

Device grade ultrashallow p+ junctions have been fabricated by a novel ion implantation scheme. The novelty of the method is in using antimony to amorphize silicon prior to a low‐energy boron implantation. Antimony satisfies a combination of two requirements lacking from all previously applied preamorphization schemes. First, due to the heavy mass of antimony, amorphization of silicon is achieved with a minimal amount of implantation damage. Second, and most important, antimony is a dopant of an opposite type than boron. Because of this, the inevitable implant tail of the preamorphizing species serves to confine the depth of the p layer. The optimized conditions for the application of this scheme have been determined. Junctions below 100 nm in depth, with less than 200 Ω/⧠ sheet resistance and junction leakage of 10 nA/cm2, have been achieved. The electrical results have been correlated with the residual defect structure observed by cross‐sectional transmission electron microscopy.

Design issues for SiGe heterojunction bipolar transistors

Recent progress in the growth of strained SiGe epitaxial layers, demonstrating the feasibility of silicon-based heterojunction transistors, is examined. The specific design issues for SiGe HBTs are discussed. These are illustrated by reviewing the experimentally obtained electrical characteristics of recent SiGe-based devices. Analytical and numerical calculations are used to explain the device physics and to assess the potential circuit advantage of SiGe for present and future technologies. Experimental results for a double-polysilicon structure with a non-self-aligned emitter opening are reported. For this type of device the additional degree of freedom available for profile optimization can be employed to enhance f/sub T/, shift the peak f/sub T/ to lower current density, or lower the base sheet resistance. Very good DC operation has been observed at room and low temperature, suggesting improved speed performance over homojunction devices.<<ETX>>

Phase edge lithography for sub 0.1 /spl mu/m electrical channel length in a 200 mm full CMOS process

In this work a deep-UV stepper is used in conjunction with a phase edge mask to define sub 0.1 /spl mu/m electrical channel length gates in a 200 mm integrated CMOS process. Conventional binary intensity mask deep-UV and mid-UV lithography are other used for other levels. We demonstrate excellent channel length control with the phase edge technique, at channel lengths here-to-fore only achievable by e-beam or X-ray lithography.

As+ and Ga+ implantation and the formation of buried GaAs layers in silicon

A buried layer of GaAs was formed in single‐crystal silicon by dual implantation of extremely high doses of As+ plus Ga+ at 200 keV, followed by furnace annealing. The layer consists of polycrystalline grains with random orientation. Rapid thermal annealing, in the presence of oxygen, does not result in the formation of GaAs. Instead, Ga and As migrate to the surface to form an oxidized layer, which is separated from the underlying silicon by a thin layer of SiO2. Analysis of the samples with single implants of Ga+ or As+ indicates the oxides formed to be Ga2O3 and As2O2. Samples implanted with As+ alone have essentially dislocation loops after annealing, while those implanted with only Ga+ have mostly microtwins and precipitates. Up to 88% Ga and 62% As from the single implants and 31% As and Ga from the dual implants are lost during annealing. This is probably due to the migration of the implanted species to the surface and the subsequent formation of volatile oxides. However, such outward migration doe...

Effects of Indium Preamorphization on Boron Implanted Silicon Annealed by RTA

Preamorphization by indium of boron implanted silicon layers has been studied as a means of reducing defects in the annealed and activated shallow junctions. The In preamorphized samples after RTP annealing at 950 to 1150°C show an absence of spanning dislocations. A 5 sec. anneal at 1100 °C results in the complete annihilation of residual dislocation loops at the original crystalline/amorphous (c/a) interface. The minimum dose to preamorphize Si with 200keV In was 5×10 13 /cm 2 . During annealing the In was found to localize at two peaks, one at the original c/a interface and the other closer to the surface, where In precipitation was observed.

Enhanced Diffusion During Rapid Thermal Annealing Of Indium And Boron In Double Implanted Silicon

Experimental results on the diffusion and precipitation of In and B doubly implanted into Si, followed by rapid thermal treatment are reported. It was observed that In redistributes itself and accumulates in defected regions. The amount of motion of each species is enhanced by the presence of the other. While the B influences In diffusion probably through the same mechanism that leads to concentration enhancement, the effect of In on B is not clear. There is no correlation with strain and no apparent chemical effects. Also the presence of B facilitates the sweeping out of In during low temperature solid phase regrowth.