George D. Gristede

Low-power circuits and technology for wireless digital systems

As CMOS technology scales to deep-submicron dimensions, designers face new challenges in determining the proper balance between aggressive high-performance transistors and lower-performance transistors to optimize system power and performance for a given application. Determining this balance is crucial for battery-powered handheld devices in which transistor leakage and active power limit the available system performance. This paper explores these questions and describes circuit techniques for low-power communication systems which exploit the capabilities of advanced CMOS technology.

Convergence properties of waveform relaxation circuit simulation methods

A new method for the analysis and understanding of the convergence properties of the waveform relaxation (WR) circuit simulation method is derived. The method describes the convergence properties of WR through a continuous-time linear time-varying (LTV) system convergence equation. From the LTV convergence equation, new sufficient conditions for the convergence of WR are derived that are less restrictive than those of all known previous work. The new sufficient conditions are shown to be valid both for the case of an exact solution of the circuit differential equations and the real-life case of an approximate numerical solution of these equations. An example is given, illustrating the application of the LTV convergence equation and comparing the new sufficient conditions for convergence of the WR method against previous work.

POWER8 design methodology innovations for improving productivity and reducing power

The design complexity of modern high performance processors calls for innovative design methodologies for achieving time-to-market goals. New design techniques are also needed to curtail power increases that inherently arise from ever increasing performance targets. This paper describes new design approaches employed by the POWER8 processor design team to address complexity and power consumption challenges. Improvements in productivity are attained by leveraging a new and more synthesis-centric design methodology. New optimization strategies for synthesized macros allow power reduction without sacrificing performance. These methodology innovations contributed to the industry leading performance of the POWER8 processor. Overall, POWER8 delivers a 2.5x increase in per-socket performance over its predecessor, POWER7+, while maintaining the same power dissipation.

Power reduction by aggressive synthesis design space exploration

An increasing focus on design productivity is shifting microprocessor design to more synthesis-centric design methodologies. Low power design is also rising in importance, even for higher performance server chips. This paper proposes a design methodology capitalizing on the relatively low cost of parallel synthesis job submission for design space exploration. By tailoring the design flow for parallel and iterative design space exploration we attempt to maximize the return on investment (ROI) of design effort. The methodology was applied to the IBM POWER7+™ microprocessor to save power during the second release of the chip. This paper provides an overview of the methodology as well as chip hardware measurements showing power savings.

Characterization of logic circuit techniques and optimization for high-leakage CMOS technologies

Channel subthreshold and gate leakage currents are predicted by many to become much more significant in advanced CMOS technologies and are expected to have a substantial impact on logic circuit design strategies. To reduce static power, techniques such as the use of monotonic logic and management of various evaluation and idle modes within logic stages may become important options in circuit optimization. In this paper, we present a general, multilevel model for logic blocks consisting of logic gates that include a wide range of options for static power reduction, in both the domains of topology and timing. Existing circuit techniques are classified within this framework and experiments are presented showing how aspects of performance might vary across this range in a hypothetical technology. The framework also allows exploration of optimal mixing of techniques.

Mixed multi-threshold differential cascode voltage switch (MT-DCVS) circuit styles and strategies for low power VLSI design

This paper presents mixed multi-threshold differential cascode voltage switch (MT-DCVS) circuits for low-power, high performance and deep-submicron VLSI design. These logic circuits incorporate two different sets of CMOS devices, low-V/sub t/ and regular high-V/sub t/ CMOS devices. By appropriately selecting the low-V/sub t/ and high-V/sub t/ devices and configurations in a circuit, we can gain performance of circuit while keeping the leakage current and power low. The key approaches are using low-V/sub t/ devices to gain performance, using high-V/sub t/ devices to cut off the leakage path and also using the reverse-biased low-V/sub t/ devices in their standby state. The methodology and algorithm are developed and simulated. The applications of such multi-V/sub t/ circuit techniques to the static, domino NORA DCVS and delayed reset circuits are described. The use of footer/header devices, gated-Vdd and a mixture of low-V/sub t/ and high-V/sub t/ devices to reduce power dissipation and subthreshold leakage current during standby and active modes, and the global design issues are also discussed.

A synthesis-parameter tuning system for autonomous design-space exploration

Advanced logic and physical synthesis tools provide a vast number of tunable parameters that can significantly impact physical design quality, but the complexity of the parameter design space requires intelligent search algorithms. To fully utilize the optimization potential of these tools, we propose SynTunSys, a system that adds a new level of abstraction between designers and design tools for managing the design space exploration process. SynTunSys takes control of the synthesis-parameter tuning process, i.e., job submission, results analysis, and next-step decision making, by automating a key portion of a human designers decision process. We present the overall organization of SynTunSys, describe its main components, and provide results from employing it for the design of an industrial chip, the IBM z13 22nm high-performance server chip. During this major design, SynTunSys provided significant savings in human design effort and achieved a quality of results beyond what human designers alone could achieve, yielding on average a 36% improvement in total negative slack and a 7% power reduction.

Characterization of logic circuit techniques for high leakage CMOS technologies

Channel subthreshold and gate leakage currents are predicted by many to become much more significant in advanced CMOS technologies and are expected to have a substantial impact on logic circuit design strategies. To reduce static power, techniques such as the use of monotonic logic and management of various evaluation and idle modes within logic stages may become important options in circuit optimization. In this paper, we present a general, multilevel model for logic blocks consisting of logic gates that include a wide range of options for static power reduction, in both the domains of topology and timing. Existing circuit techniques are classified within this framework and experiments are presented showing how aspects of performance might vary across this range in a hypothetical technology. The framework also allows exploration of optimal mixing of techniques.Channel subthreshold and gate leakage currents are predicted by many to become much more significant in advanced CMOS technologies and are expected to have a substantial impact on logic circuit design strategies. To reduce static power, techniques such as the use of monotonic logic and management of various evaluation and idle modes within logic stages may become important options in circuit optimization. In this paper, we present a general, multilevel model for logic blocks consisting of logic gates that include a wide range of options for static power reduction, in both the domains of topology and timing. Existing circuit techniques are classified within this framework and experiments are presented showing how aspects of performance might vary across this range in a hypothetical technology. The framework also allows exploration of optimal mixing of techniques.

A comparison of dual-rail pass transistor logic families in 1.5V, 0.18μm CMOS technology for low power applications

In this paper the results of an experimental comparison of popular pass-transistor logic families in 1.5V, 0.18µm CMOS technology using advanced CAD tools for circuit tuning and simulation are presented. The logic families were compared using an experimental setup designed to clarify the strengths and weaknesses of each family in a relative fashion and evaluate their individual performances under identical operating conditions. An automatic circuit tuner was used to help ensure that the test circuits from each logic family were operating at near optimum performance. It is shown that the Differential Cascode Voltage Switch with Pass-Gate (DCVSPG) logic family is the most robust with respect to an amalgamation of speed, power, area and physical design criteria. The methodology of using hybrid pass-transistor / static CMOS circuit styles is also presented.

The opportunity cost of low power design: a case study in circuit tuning

The time-to-market pressures combined with the immense power reduction design space of VLSI design call for an evaluation of power savings opportunities prior to the investment in design effort. This paper presents an estimation methodology for predicting the power savings of circuit tuning for an industrial chip design project. A comparison between the estimated and actual power savings realized through tuning over 100 macros on the chip validates the accuracy of this estimation methodology.