Christophe Tretz

High-Density Reduced-Stack Logic Circuit Techniques Using Independent-Gate Controlled Double-Gate Devices

Novel high-density logic-circuit techniques employing independent-gate controlled double-gate (DG) devices are proposed. The scheme utilizes the threshold-voltage (VT) difference between double-gated and single-gated modes in a high-VT DG device to reduce the number of transistors required to implement the stack logic. In a series-connected stack portion of the logic gate, the number of transistors is halved, thus substantially improving the area/capacitance and the circuit performance. The scheme can be easily implemented by a DG technology with either a metal gate or a polysilicon gate. Six-way logic can be implemented with the proposed scheme using only six transistors. The viability and performance advantage of the scheme are validated via extensive mixed-mode physics-based numerical simulations

Novel high-density low-power logic circuit techniques using DG devices

Novel high-density low-power double-gate circuit techniques for basic logic families such as NAND, NOR, and pass-gate are proposed. The technique exploits the independent front- and back-gate bias to reduce the number of transistors for implementing logic functions. The scheme substantially improves the standby and dynamic power consumptions by reducing the number of transistors and the chip area/size while improving the circuit performance. The power/performance advantages are analyzed/validated via mixed-mode two-dimensional MEDICI numerical device simulations, as well as by using physical delay equations.

Novel high-density low-power high-performance double-gate logic techniques

This paper propose novel double-gate (DG) logic circuit schemes using only symmetrical gates to reduce the area and leakage/active power. The performance improvement and power reduction for NAND, NOR, and pass-gate are studied via the two-dimensional numerical device simulator to directly simulate the circuit structures.

Ratioed CMOS: a low power high speed design choice in SOI technologies

Ratioed CMOS gates implemented in a partially-depleted (PD) SOI CMOS technology are usually considered to be high power but end up being both faster and lower power than other circuit implementations, mainly due to the reduced junction capacitance in SOI devices as well as floating-body effects. As an example, a high performance multiplier shifter is 3 to 4 times faster and dissipates 9 times less power than more conventional implementations.

Performance comparison of differential static CMOS circuit topologies in SOI technology

This paper examines the performance of differential static CMOS circuit topologies based on partially-depleted (PD) and dual-gate SOI devices. Both device types have L/sub eff/=0.15 /spl mu/m. The top and bottom gates of the dual-gate device are self-aligned to the source/drain, and the device has a fanned-out source/drain structure with low parasitic resistance. The dual-gate device current drive and transconductance are about 2.2 times that of a partially-depleted device at the same bias. We compared three differential static CMOS topologies: (a) standard CMOS logic; (b) push-pull cascode logic (PPCL), a low power high speed static logic topology; (c) complementary pass-transistor logic (CPL), known for its efficiency for device use and popular for fast arithmetic operations. We considered three cases: (a) partially-depleted device with standard bulk-like connection where the body is tied to the supply rail; (b) partially-depleted device with floating body (FB); (c) dual gate (DG) device where the bottom gate is driven with the top gate simultaneously. Based on a methodology described previously (Tretz et al. Proc. IEEE Midwest Symp. on Circuits and Systems, pp. 179-82, 1996), performance comparison of these topologies is sufficient to establish the relative performance of almost any other differential static CMOS topology, using the generic differential CMOS static gate concept. All differential static circuits can be described as a variation of the generic differential static gate comprised of pull-up and pull-down switches, cross-coupled elements, additional resistive loads, and active paths to V/sub dd//GND.

An all digital frequency-locked loop immune to hysteresis effects for power management of multicore processors

Low power design has always been critical to high performance. With the latest technologies, being able to significantly reduce any portion of the overall system power becomes an absolute requirement for extending the lifetime of the system. Clock generation and clock tree distribution are always identified as a significant portion of the power dissipated in a chip. We describe here a servocontrol circuit method that will provide both a lower power clock generation scheme as well as automated power management using the clock elements. The self correcting nature of the circuits proposed also offer good immunity against hysteresis effects.

Metastability of SOI CMOS latches

An analysis of the metastability of silicon-on-insulator (SOI) complementary metal-oxide-silicon (CMOS) latches is presented, using partially-depleted SOI devices with various body-connection topologies and an unbuffered latch. The metastability window, resolution time and time interval between the clock edge and the time t meta are evaluated as functions of power supply and the type of body-connection topology. Simulations using SOISPICE show improved metastability behaviour for SOI specific body-connection topologies.

Optimal Design of Nanoscale Triple-Gate Devices

The impacts of corner rounding in TG MOSFETs on DIBL and device characteristics were analyzed via 3D numerical simulations. Properly rounded corners of TG device can improve SCEs or increase drive current. Semi-cylindrical gate structure is preferable for heavily-doped devices, while rectangular gate structure appears better for lightly-doped devices, respectively

High-density logic techniques with reduced-stack double-gate MOSFETs

We have presented a high-density DG logic circuit technique exploiting the unique V/sub T/ modulation effect through the extended gate-to-gate coupling in high-V/sub T/ symmetrical DG devices. The scheme reduces the number of stacked transistors (hence area/capacitance and standby/dynamic power), and improves performance. The performance improvement and power reduction are evaluated/validated using mixed-mode two-dimensional numerical simulations.

Fine-grained power managed dual-thread vector scalar unit for the first-generation CELL processor

This paper describes the design and implementation of the vector scalar unit (VSU) in the first-generation CELL processor. VSU executes floating-point and vector media extension instructions. VSU contains 1.7 million transistors and occupies an area of 3.1 mm/sup 2/ in a 90nm PD-SOI technology. Extensive static and dynamic circuit techniques are used to optimize performance while minimizing area and power simultaneously. Full functionality is observed at 4.76 GHz, 1.3V supply and a chip temperature of 68/spl deg/C.