Matthew M. Ziegler

CMOS/nano co-design for crossbar-based molecular electronic systems

Future electronic systems will need to adopt novel nanoelectronic solutions to keep pace with Moores Law. Crossbar-based molecular electronics are among the most promising of nanotechnologies. However, circuits similar to the conventional mainstream electronics of today will have a presence in future complex systems for some time. This paper presents a circuit paradigm where silicon and molecular electronics are integrated. We discuss methods for realizing memory and logic using nanoscale crossbars as well as for interfacing the crossbars to CMOS circuitry. Using custom nanoscale device models, we perform circuit simulation and analysis of the crossbar circuits and the peripheral CMOS circuitry. Finally, we present a design methodology to accompany the CMOS/nano paradigm.

Design and analysis of crossbar circuits for molecular nanoelectronics

We consider crossbar structures for nanoelectronics from a circuit design perspective. Given the large design space and the many promising nanotechnologies, we develop parameterized circuit models for quickly surveying the crossbar design space. We then present methods for implementing logic and memory in crossbars via a programmed decoder. Finally, we consider the implications of logic representation when mapping circuits to crossbars.

A Sub-600-mV, Fluctuation Tolerant 65-nm CMOS SRAM Array With Dynamic Cell Biasing

Fluctuation limitations on scaling CMOS SRAM cell transistor dimensions and operating voltages are demonstrated by measuring local stochastic distributions of 65-nm PDSOI CMOS SRAM cell storage node voltages during read, write, and retention modes of operation. These measurements reveal insights into terminal voltage dependencies of cell margin distributions - observations that are engaged to increase cell immunity to random VT fluctuations by several orders of magnitude by biasing the cell terminal voltages dynamically with a read-write asymmetry. Combinations of circuit techniques implementing these dynamic cell biasing schemes are demonstrated in a 9 kb times74 b PDSOI CMOS SRAM array with a conventional 65 nm SRAM cell and an ABIST. Measurements demonstrate these techniques to enable VMIN reductions of over 200 mV - lowering measured VMIN to 0.54 V and 0.38 V/0.50 V for single and dual VDD implementations, respectively. The techniques consume a 10%-12% overhead in area, impact performance marginally (<5%) and also enable over 50% reduction in cell leakage.

A case for CMOS/nano co-design

The challenge of extending Moores Law past the physical and economic barriers of present semiconductor technologies calls for novel nanoelectronic solutions. Circuits composed of mixed silicon semiconductors and nanoelectronics can provide a means for gradually switching technology paradigms. We suggest a design methodology to accompany this concept. Furthermore, we explore design tradeoffs for a nanoscale crossbar technology that supports CMOS/nano co-design.

The CMOS/nano interface from a circuits perspective

We consider a circuit paradigm that combines conventional silicon microelectronics with emerging self-assembled nanoelectronics. Peripheral CMOS circuitry is used to drive the input signals and restore the output signals of nanoscale crossbar structures. We address a number of issues dealing with interfacing CMOS and nanoelectronics. Furthermore, we consider important metrics, such as, delay, area, and energy for a full-adder implemented in the mixed circuit paradigm.

Scalability Simulations for Nanomemory Systems Integrated on the Molecular Scale

Abstract: Simulations were performed to assess the prospective performance of a 16 Kbit nanowire‐based electronic nanomemory system. Commercial off‐the‐shelf microcomputer system modeling software was applied to evaluate the operation of an ultra‐dense storage array. This array consists of demonstrated experimental non‐volatile nanowire diode switches, plus encoder‐decoder structures consisting of demonstrated experimental nanowire‐based nanotransistors, with nanowire interconnects among all the switching devices. The results of these simulations suggest that a nanomemory of this type can be operated successfully at a density of 1011 bits/cm2. Furthermore, modest device alterations and system design alternatives are suggested that might improve the performance and the scalability of the nanomemory array. These simulations represent early steps toward the development of a simulation‐based methodology to guide nanoelectronic system design in a manner analogous to the way such methodologies are used to guide microelectronic system design in the silicon industry.

A unified design space for regular parallel prefix adders

We consider sparsity, fanout, and radix as three dimensions in the design space of regular parallel prefix adders and present a unified formalism to describe such structures.

A universal device model for nanoelectronic circuit simulation

As nanoelectronics approaches the maturity needed for circuit level integration we will need modeling approaches that can capture non-classical behaviors in a compact manner. We propose a universal device model (UDM) that addresses the challenge of correctly balancing accuracy, complexity, and flexibility. The UDM qualitatively represents fundamental classical and quantum phenomena such that nanoelectronic circuit design and simulation become possible. We discuss the motivation behind this modeling approach as well as the underlying details of the model. Furthermore, we present circuit examples of the model in action.

Large-signal two-terminal device model for nanoelectronic circuit analysis

As the nanoelectronics field reaches the maturity needed for circuit-level integration, modeling approaches are needed that can capture nonclassical behaviors in a compact manner. This paper proposes a universal device model (UDM) for two-terminal devices that addresses the challenge of correctly balancing accuracy, complexity, and flexibility. The UDM qualitatively captures fundamental classical and quantum phenomena and enables nanoelectronic circuit design and simulation. We discuss the motivation behind this modeling approach as well as the underlying details of the model. Furthermore, we present a circuit example of the model in action.

Architectures and Simulations for Nanoprocessor Systems Integrated on the Molecular Scale

This chapter concerns the design, development, and simulation of nanoprocessor systems integrated on the molecular scale. It surveys ongoing re- search and development on nanoprocessor architectures and discusses challenges in the implementation of such systems. System simulation is used to identify some advantages, issues, and trade-offs in potential implementations. Previously, the au- thors and their collaborators considered in detail the requirements and likely per- formance of nanomemory systems. This chapter recapitulates the essential aspects of that earlier work and builds upon those efforts to examine the likely architectures and requirements of nanoprocessors. For nanoprocessor systems, simulation, as well as design and fabrication, embodies unique problems beyond those introduced by the large number of densely-packed, novel nanodevices. For example, unlike the largely homogeneous structure of circuitry in nanomemory arrays, a high degree of variety and inhomogeneity must be present in nanoprocessors. Also, issues of clocking, signal restoration, and power become much more significant. Thus, build- ing and operating nanoprocessor systems will present significant new challenges and require additional innovations in the application of molecular-scale devices and circuits, beyond those already achieved for nanomemories. New nanoelectronic de- vices, circuits, and architectures will be necessary to perform the more complex and specialized functions inherent in processing systems at the nanometer scale. This chapter highlights the fundamental design requirements of such nanoprocessor systems, presents various device and design options, and discusses their potential implications for system performance.