George E. Bailey

Double pattern EDA solutions for 32nm HP and beyond

The fate of optical-based lithography hinges on the ability to deploy viable resolution enhancement techniques (RET). One such solution is double patterning (DP). Like the double-exposure technique, double patterning is a decomposition of the design to relax the pitch that requires dual masks, but unlike double-exposure techniques, double patterning requires an additional develop and etch step, which eliminates the resolution degradation due to the cross-coupling that occurs in the latent images of multiple exposures. This additional etch step is worth the effort for those looking for an optical extension [1]. The theoretical k1 for a double-patterning technique of a 32nm half-pitch (HP) design for a 1.35NA 193nm imaging system is 0.44 whereas the k1 for a single-exposure technique of this same design would be 0.22 [2], which is sub-resolution. There are other benefits to the DP technique such as the ability to add sub-resolution assist features (SRAF) in the relaxed pitch areas, the reduction of forbidden pitches, and the ability to apply mask biases and OPC without encountering mask constraints. Similarly to AltPSM and SRAF techniques one of the major barriers to widespread deployment of double patterning to random logic circuits is design compliance with split layout synthesis requirements [3]. Successful implementation of DP requires the evolution and adoption of design restrictions by specifically tailored design rules. The deployment of double patterning does spawn a couple of issues that would need addressing before proceeding into a production environment. As with any dual-mask RET application, there are the classical overlay requirements between the two exposure steps and there are the complexities of decomposing the designs to minimize the stitching but to maximize the depth of focus (DoF). In addition, the location of the design stitching would require careful consideration. For example, a stitch in a field region or wider lines is preferred over a transistor region or narrower lines. The EDA industry will be consulted for these sound automated solutions to resolve double-patterning sensitivities and to go beyond this with the coupling of their model-based and process-window applications. This work documented the resolution limitations of single exposure, and double-patterning with the latest hyper-NA immersion tools and with fully optimized source conditions. It demonstrated the best known methods to improve design decomposition in an effort to minimize the impact of mask-to-mask registration and process variance. These EDA solutions were further analyzed and quantified utilizing a verification flow.

Intensive 2D SEM model calibration for 45nm and beyond

Conventional site-base model calibration approaches have worked fine from the 180nm down to the 65nm technology nodes, but with the first 45nm technology nodes rapidly approaching, site-based model calibration techniques may not capture the details contained in these 2D-intensive designs. Due to the compaction of designs, we have slowly progressed from 1D-intensive gates, which were site-based friendly, to very complex and sometimes ornate 2D-gate regions. To compound the problem, these 2D-intensive gate regions are difficult to measure resulting in metrology-induced error when attempting to add these regions to the model calibration data. To achieve the sub-nanometer model accuracy required at this node, a model calibration technique must be able to capture the curvature induced by the process and the design in these gate regions. A new approach in model calibration had been developed in which images from a scanning electron microscope (SEM) are used together with the conventional site-base to calibrate models instead of the traditional single critical dimension (CD) approach. The advantage with the SEM-image model calibration technique is that every pixel in the SEM image contributes as CD information improving model robustness. Now the ornate gate regions could be utilized as calibration features allowing the acquisition of fine curvature in the design. This paper documents the issues of the site-base model calibration technique at the 45nm technology node and beyond. It also demonstrates the improvement in model accuracy for critical gate regions over the traditional modeling technique, and it shows the best know methods to achieve the utmost accuracy. Lastly, this paper shows how SEM-based modeling quantifies modeling error in these complex 2D regions.

Source polarization and OPC effects on illumination optimization

To perform a thorough source optimization during process development is becoming more critical as we move to leading edge-technology nodes. With each new node the acceptable process margin continues to shrink as a result of lowering k1 factors. This drives the need for thorough source optimization prior to locking down a process in order to attain the maximum common depth of focus (DOF) the process will allow. Optical proximity correction (OPC) has become a process-enabling tool in lithography by providing a common process window for structures that would otherwise not have overlapping windows. But what effect does this have on the source optimization? With the introduction of immersion lithography there is yet another parameter, namely source polarization, that may need to be included in an illumination optimization process. This paper explored the effect polarization and OPC have on illumination optimization. The Calibre ILO (Illumination Optimization) tool was used to perform the illumination optimization and provided plots of DOF vs. various parametric illumination settings. This was used to screen the various illumination settings for the one with optimum process margins. The resulting illumination conditions were then implemented and analyzed at a full chip level. Based on these results, a conclusion was made on the impact source polarization and OPC would have on the illumination optimization process.

Feedback flow to improve model-based OPC calibration test patterns

Process models are responsible for the prediction of the latent image in the resist in a lithographic process. In order for the process model to calculate the latent image, information about the aerial image at each layout fragment is evaluated first and then some aerial image characteristics are extracted. These parameters are passed to the process models to calculate wafer latent image. The process model will return a threshold value that indicates the position of the latent image inside the resist, the accuracy of this value will depend on the calibration data that were used to build the process model in the first place. The calibration structures used in building the models are usually gathered in a single layout file called the test pattern. Real raw data from the lithographic process are measured and attached to its corresponding structure in the test pattern, this data is then applied to the calibration flow of the models. In this paper we present an approach to automatically detect patterns that are found in real designs and have considerable aerial image parameters differences with the nearest test pattern structure, and repair the test patterns to include these structures. This detect-and-repair approach will guarantee accurate prediction of different layout fragments and therefore correct OPC behavior.

Dark-field high-transmission chromeless lithography

Dark field (i.e. hole and trench layer) lithographic capability is lagging that of bright field. The most common dark field solution utilizes a biased-up, standard 6% attenuated phase shift mask (PSM) with an under-exposure technique to eliminate side lobes. However, this method produces large optical proximity effects and fails to address the huge mask error enhancement factor (MEEF) associated with dark field layers. It also neglects to provide a dark field lithographic solution beyond the 130nm technology node, which must serve two purposes: 1) to increase resolution without reducing depth of focus, and 2) to reduce the MEEF. Previous studies have shown that by increasing the background transmission in dark field applications, a corresponding decrease in the MEEF was observed. Nevertheless, this technique creates background leakage problems not easily solved without an effective opaqueing scheme. This paper will demonstrate the advantages of high transmission lithography with various approaches. By using chromeless dark field scattering bars around contacts for image contrast and chromeless diffraction gratings in the background, high transmission dark field lithography is made possible. This novel layout strategy combined with a new, very high transmission attenuating layer provides a dark field PSM solution that extends 248nm lithography capabilities beyond what was previously anticipated. It is also more manufacturing-friendly in the mask operation due to the absence of tri-tone array features.

Safe interpolation distance for VT5 resist model

As the technology shrinks toward 65nm technology and beyond, Optical Proximity Correction (OPC) becomes more important to insure proper printability of high-performance integrated circuits. This correction involves some geometrical modifications to the mask polygons to account for light diffraction and etch biasing. Model-based OPC has proven to be a convenient, accurate, and efficient methodology. In this method, raw calibration data are measured from the process. These data are used to build a VT5 resist model [1] that accounts for all proximity effects that attendant to the lithography process. To ensure the reliability of the calibrated VT5 model, these data must be broad in the image parameter space (IPS) to account for different one-dimensional and two-dimensional features for the design intent. Failure to provide sufficient IPS (i.e. mimic the design intent) coverage during model calibration could result in marginalizing the VT5 model during OPC, but is difficult to judge when there is enough data volume to safely interpolate and extrapolate design intent. In this paper we introduce a new metric called Safe Interpolation Distance (SID). This metric is a multi-dimensional metric which can be used to automatically detect the portions of the target design that are not covered well by the desired VT5 model.

Circuit-based SEM Contour OPC Model Calibration

In order to achieve the necessary OPC model accuracy, the requisite number of SEM CD measurements has exploded with each technology generation. At 65 nm and below, the need for OPC and/or manufacturing verification models for several process conditions (focus, exposure) further multiplies the number of measurements required. SEM-contour based OPC model calibration has arisen as a powerful approach to deliver robust and accurate OPC models since every pixel now adds information for input into the model, substantially increasing the parameter space coverage. To date however, SEM contours have been used to supplement the hundreds or thousands of discreet CD measurements to deliver robust and accurate models. While this is still perhaps the optimum path for high accuracy, there are some cases where OPC test patterns are not available, and the use of existing circuit patterns is desirable to create an OPC model. In this work, SEM contours of in-circuit patterns are utilized as the sole data source for OPC model calibration. The use scenario involves 130 nm technology which was initially qualified for production with the use of rule-based OPC, but is shown to benefit from model based OPC. In such a case, sub-nanometer accuracy is not required, and in-circuit features can enable rapid development of sufficiently accurate models to provide improved process margin in manufacturing.

Distributed processing in integrated data preparation flow

The era of week-long turn around times (TAT) and half-terabyte databases is at hand as seen by the initial 90 nm production nodes. A quadrupling of TAT and database volumes for the subsequent nodes is considered to be a conservative estimate of the expected growth by most mask data preparation (MDP) groups, so how will fabs and mask manufacturers address this data explosion with a minimal impact to cost? The solution is a multi-tiered approach of hardware and software. By shifting from costly Unix servers to cheaper Linux clusters, MDP departments can add hundreds to thousands of CPU’s at a fraction of the cost. This hardware change will require the corresponding shift from multithreaded (MT) to distributed-processing tools or even a heterogeneous configuration of both. Can the EDA market develop the distributed-processing tools to support the era of data explosion? This paper will review the progression and performance (run time and scalability) of the distributed-processing MDP tools (DRC, OPC, fracture) along with the impact to the hierarchy preservation. It will consider the advantages of heterogeneous processing over homogenous. In addition, it will provide insight to potential non-scalable overhead components that could eventually exist in a distributed configuration. Lastly, it will demonstrate the cost of ownership aspect of the Unix and Linux platforms with respect to targeting TAT.

SEM based data extraction for model calibration

The model calibration process, in a resolution enhancement technique (RET) flow, is one of the most critical steps towards building an accurate OPC recipe. RET simulation platforms use models for predicting latent images in the wafer due to exposure of different design layouts. Accurate models can precisely capture the proximity effects for the lithographic process and help RET engineers build the proper recipes to obtain high yield. To calibrate OPC models, test geometries are created and exposed through the lithography environment that we want to model, and metrology data are collected for these geometries. This data is then used to tune or calibrate the model parameters. Metrology tools usually provide critical dimension (CD) data and not edge placement error (EPE - the displacement between the polygon and resist edge) data however model calibration requires EPE data for simulation. To work around this problem, only symmetrical geometries are used since, having this constraint, EPE can be easily extracted from CD measurements. In real designs, it is more likely to encounter asymmetrical structures as well as complex 2D structures that cannot easily be made symmetrical, especially when we talk about technology nodes for 65nm and beyond. The absence of 2D and asymmetric test structures in the calibration process would require models to interpolate or extrapolate the EPEs for these structures in a real design. In this paper we present an approach to extract the EPE information from both SEM images and contours extracted by the metrology tools for structures on test wafers, and directly use them in the calibration of a 55nm poly process. These new EPE structures would now mimic the complexity of real 2D designs. Each of these structures can be individually weighed according to the data variance. Model accuracy is then compared to the conventional method of calibration using symmetrical data only. The paper also illustrates the ability of the new flow to extract more accurate measurement out of wafer data that are more immune to errors compared to the conventional method.

EMF simulation with DDM to enable EAPSM masks in 45-nm manufacturing

One of the enabling RET candidates for 45 nm robust imaging is high transmission (20-30%) EAPSM masks. However, the effectiveness of these masks is strongly affected by the electromagnetic field (EMF) that is ignored in most commercial full-chip OPC applications that rely on the Kirchhoff approximation. This paper utilizes new commercial software to identify and characterize points in a design that are especially sensitive to these EMF effects. Characterization of conventional 6% and 30% High Transmission photomasks were simulated and compared with experimental results. We also explored, via simulation-driven design of experiment, the impact of mask variations in transmission, phase, and SRAF placement and size to the imaging capability. The simulations are confirmed by producing a photomask including the experimental variations and printing the mask to silicon. Final analysis of the data will include exact mask measurements to confirm match to simulation assumptions of mask stack, and phase.