Ali Afzali

High-mobility ultrathin semiconducting films prepared by spin coating.

The ability to deposit and tailor reliable semiconducting films (with a particular recent emphasis on ultrathin systems) is indispensable for contemporary solid-state electronics. The search for thin-film semiconductors that provide simultaneously high carrier mobility and convenient solution-based deposition is also an important research direction, with the resulting expectations of new technologies (such as flexible or wearable computers, large-area high-resolution displays and electronic paper) and lower-cost device fabrication. Here we demonstrate a technique for spin coating ultrathin (∼50 Å), crystalline and continuous metal chalcogenide films, based on the low-temperature decomposition of highly soluble hydrazinium precursors. We fabricate thin-film field-effect transistors (TFTs) based on semiconducting SnS2-xSex films, which exhibit n-type transport, large current densities (>105 A cm-2) and mobilities greater than 10 cm2 V-1 s-1—an order of magnitude higher than previously reported values for spin-coated semiconductors. The spin-coating technique is expected to be applicable to a range of metal chalcogenides, particularly those based on main group metals, as well as for the fabrication of a variety of thin-film-based devices (for example, solar cells, thermoelectrics and memory devices).

Self-aligned carbon nanotube transistors with charge transfer doping

This letter reports a charge transfer p-doping scheme which utilizes one-electron oxidizing molecules to obtain stable, unipolar carbon nanotube transistors with a self-aligned gate structure. This doping scheme allows one to improve carrier injection, tune the threshold voltage Vth, and enhance the device performance in both the “ON-” and “OFF-” transistor states. Specifically, the nanotube transistor is converted from ambipolar to unipolar, the device drive current is increased by 2–3 orders of magnitude, the device OFF current is suppressed and an excellent Ion∕Ioff ratio of 106 is obtained. The important role played by metal–nanotube contacts modification through charge transfer is demonstrated.

Toward High-Performance Digital Logic Technology with Carbon Nanotubes

The slow-down in traditional silicon complementary metal-oxide-semiconductor (CMOS) scaling (Moores law) has created an opportunity for a disruptive innovation to bring the semiconductor industry into a postsilicon era. Due to their ultrathin body and ballistic transport, carbon nanotubes (CNTs) have the intrinsic transport and scaling properties to usher in this new era. The remaining challenges are largely materials-related and include obtaining purity levels suitable for logic technology, placement of CNTs at very tight (∼5 nm) pitch to allow for density scaling and source/drain contact scaling. This review examines the potential performance advantages of a CNT-based computing technology, outlines the remaining challenges, and describes the recent progress on these fronts. Although overcoming these issues will be challenging and will require a large, sustained effort from both industry and academia, the recent progress in the field is a cause for optimism that these materials can have an impact on future technologies.

High purity isolation and quantification of semiconducting carbon nanotubes via column chromatography.

The isolation of semiconducting carbon nanotubes (CNTs) to ultrahigh (ppb) purity is a prerequisite for their integration into high-performance electronic devices. Here, a method employing column chromatography is used to isolate semiconducting nanotubes to 99.9% purity. The study finds that by modifying the solution preparation step, both the metallic and semiconducting fraction are resolved and elute using a single surfactant system, allowing for multiple iterations. Iterative processing enables a far more rapid path to achieving the level of purities needed for high performance computing. After a single iteration, the metallic peak in the absorption spectra is completely attenuated. Although absorption spectroscopy is typically used to characterize CNT purity, it is found to be insufficient in quantifying solutions of high purity (>98 to 99%) due to low signal-to-noise in the metallic region of ultrahigh purity solutions. Therefore, a high throughput electrical testing method was developed to quantify the degree of separation by characterizing ∼4000 field-effect transistors fabricated from the separated nanotubes after multiple iterations of the process. The separation and characterization methods described here provide a path to produce the ultrahigh purity semiconducting CNT solutions needed for high performance electronics.

Operational and environmental stability of pentacene thin-film transistors

We report the effects of repeated stressing and environmental exposure on the operational stability of pentacene thin-film transistors (TFTs). Pentacene TFT channels were deposited by thermal evaporation and by spin coating and thermally converting soluble precursors. For a given dielectric thickness and applied voltage, pentacene TFTs with shorter channel lengths and therefore higher current densities have the largest decrease in field-effect mobility, on-current, and subthreshold slope and the largest threshold voltage shift with device cycling. Devices measured in ambient nitrogen show little degradation and devices fabricated on thinner dielectrics, operated at lower voltages with similarly high current densities in air, show reduced degradation. These results are consistent with degradation by thermal oxidation and suggest that reducing the operational power (by device scaling) and limiting channel exposure to ambient air improves device stability.

Self-aligned carbon nanotube transistors with novel chemical doping

We report an unconventional chemical p- and n- doping scheme utilizing novel materials and a charge transfer mechanism to obtain air-stable, self-aligned, unipolar carbon nanotube transistors. This scheme in addition to introducing the tunability of the threshold voltage V/sub th/, increases the drive current 2-3 orders of magnitude, transforms CNFET from ambipolar to unipolar, suppresses minority carrier injection and yields an excellent I/sub on//I/sub off/ ratio of 10/sup 6/.

Novel strategy for diameter-selective separation and functionalization of single-wall carbon nanotubes.

The problem of separating single-wall carbon nanotubes (CNTs) by diameter and/or chirality is one of the greatest impediments toward the widespread application of these promising materials in nanoelectronics. In this paper, we describe a novel physical-chemical method for diameter-selective CNT separation that is both simple and effective and that allows up-scaling to large volumes at modest cost. Separation is based on size-selective noncovalent matching of an appropriate anchor molecule to the wall of the CNT, enabling suspension of the CNTs in solvents in which they would otherwise not be soluble. We demonstrate size-selective separation in the 1-2 nm diameter range using easily synthesized oligo-acene adducts as a diameter-selective molecular anchor. CNT field effect transistors fabricated from diameter-selected CNTs show markedly improved electrical properties as compared to nonselected CNTs.

Directed Assembly of Single-Walled Carbon Nanotubes via Drop-Casting onto a UV-Patterned Photosensitive Monolayer

We report the use of a novel UV-sensitive self-assembled monolayer to selectively deposit single-walled carbon nanotubes from solution using heterogeneous surface wettability. This process combines ubiquitous photopatterning techniques with simple solution processing to yield highly selective and densely packed carbon nanotube patterns. The essential concept behind this process is the change in surface chemistry caused by the UV-induced monolayer reaction. Selective deposition of carbon nanotubes was achieved by drop-casting, and the resulting films show local ordering, indicating that further development of this process will lead to simple technique for large-scale integration.

Optimization of pH sensing using silicon nanowire field effect transistors with HfO2 as the sensing surface

Silicon nanowire field effect transistor sensors with SiO(2)/HfO(2) as the gate dielectric sensing surface are fabricated using a top down approach. These sensors are optimized for pH sensing with two key characteristics. First, the pH sensitivity is shown to be independent of buffer concentration. Second, the observed pH sensitivity is enhanced and is equal to the Nernst maximum sensitivity limit of 59 mV/pH with a corresponding subthreshold drain current change of ∼ 650%/pH. These two enhanced pH sensing characteristics are attributed to the use of HfO(2) as the sensing surface and an optimized fabrication process compatible with silicon processing technology.

Device scaling in sub-100nm pentacene field-effect transistors

Reported here is the fabrication of 20–100nm channel length pentacene field-effect transistors (FETs) with well-behaved current-voltage characteristics. Using a solution deposition method, pentacene grains span entire devices, providing superior contacts. Varying the gate oxide thickness, the effects of scaling on transistor performance is studied. When the channel length to oxide thickness exceeds 5:1, electrostatically well-scaled nanometer FETs are prepared. The results show that the device characteristics are dominated by the contacts. Decreasing the oxide thickness lowers the device turn-on voltage beyond simple field scaling, as sharper bending of the gate potential lines around the contacts more effectively reduces the molecule/source interfacial resistance.