Piet Wambacq

Single-package integration of RF blocks for a 5 GHz WLAN application

Transceivers for future digital telecommunications applications (third generation cellular, wireless LAN) need to be portable (compact), battery-powered and wireless. Todays single-chip solutions for RF front-ends do not yield complete system integration. For example, they typically still need external components for impedance matching, for antenna switches, for power amplifiers and for RF bandpass filters (BPFs). Furthermore, problems of substrate coupling (either manifesting as analog crosstalk or as noise coupling from the digital part to the analog part on mixed-signal chip) become more important with increasing integration. A system-in-a-package (SiP) approach can address these problems. High quality components can be integrated in the package, avoiding lower quality on-chip passives or circumventing expensive chip technology adaptations. Virtually all external components can be integrated, as shown in this paper for the case of the bandpass filters and the impedance matching. Even the antenna is a candidate for integration in the package. Further, a clever chip partitioning can reduce the substrate coupling problem. Partitioning also allows using the best IC-technoiogy for each component. This paper reports on a fully integrated single-package RF prototype module for a 5 GHz WLAN receiver front-end, which is intended to demonstrate the concept of SiP integration. The approach, that is illustrated here with prototype RF blocks for a 5 GHz WLAN application, is implemented with a thin film multichip module (MCM-D) interconnect technology. This technology also allows the integration of high quality passive components. With these passives, low-loss filters can be implemented. The use of passives, filters and off-the-shelf, active, bare die components opens the way to successful system integration.

Chip-package codesign of a low-power 5-GHz RF front end

Future high-performance wireless communication applications such as wireless local area networks (WLANs) around 5 GHz require low-power and highly integrated transceiver solutions. The integration of the RF front end especially poses a great challenge in these applications, as traditional front-end implementations require a large number of external passive components. In this paper, we present the single-package integration of complete transceivers based on a thin-film multichip module (MCM) technology with integrated passives. The MCM substrate is a a common carrier onto which different ICs are mounted. passive components such as RF bandpass filters, inductors, capacitors, and resistors are directly integrated into the MCM substrate with the use of the multilayer structure of the MCM technology. The system-on-a-package approach is illustrated with a voltage-controlled oscillator for Digital European Cordless Telephone (DECT) applications and a 5-GHz WLAN front end. These examples indicate that this approach yields a compact low-power implementation of complete transceivers for high-performance wireless applications.

A wideband beamformer for a phased-array 60GHz receiver in 40nm digital CMOS

For high-data-rate wireless communication in the 7GHz band around 60GHz, the IEEE 802.15.3c standard [1] provides channels with a 0.88GHz bandwidth for the AV-OFDM mode. For the single-carrier modes, the ECMA 387 standard [2] foresees the possibility of bonding together adjacent channels, yielding higher data-rates. Radios for these 60GHz standards often use phased antenna arrays to relax the link budget. A phased-array receiver needs a variable phase shift on each antenna path and a combiner that sums the signals from the individual paths after phase shifting. The beamforming circuitry presented here handles 4 paths. It can operate both with one 0.88GHz channel and with bonding of two such channels. Phase shifts are realized with a resolution better than 20°. Bandwidth is high thanks to the use of current amplifiers with very low input impedance.

A low-power 57-to-66GHz transceiver in 40nm LP CMOS with −17dB EVM at 7Gb/s

Obtaining sufficient EVM in all four 1.76GHz bandwidth chann1.76GHzels specified by IEEE 802.15.3c and the emerging 802.11ad high-data-rate wireless communication standards for modulations as complex as QAM16 is a challenge. Recently reported implementations are therefore restricted to just 1 or 2 channels. Wireless applications often use digital low-power (LP) CMOS technology to implement single-chip transceivers. The high Vt and the thin metal interconnect layers constrain the mm-Wave circuit performance. This paper presents a digital LP 40nm CMOS 60GHz transceiver (TRX) IC that obtains an EVM better than -17dB in all 4 channels.

Low-power voltage-controlled oscillators in 90-nm CMOS using high-quality thin-film postprocessed inductors

Wafer-level packaging (WLP) technology offers novel opportunities for the realization of high-quality on-chip passives needed in RF front-ends. This paper demonstrates a thin-film WLP technology on top of a 90-nm RF CMOS process with one 15-GHz and two low-power 5-GHz voltage-controlled oscillators (VCOs) using a high-quality WLP or above-IC inductor. The 5-GHz VCOs have a power consumption of 0.33 mW and a phase noise of -115 dBc/Hz and -111 dBc/Hz at 1-MHz offset, respectively, and the 15-GHz VCO has a phase noise of -105 dBc/Hz at 1-MHz offset with a power consumption of 2.76 mW.

A fifth-order 880MHz/1.76GHz active lowpass filter for 60GHz communications in 40nm digital CMOS

For the analog baseband section of a 60GHz receiver for fast download applications, two 5th order Butterworth filters with cutoff frequency of 880MHz and 1.76GHz for 60GHz radios are implemented in 40nm low power digital CMOS, using Sallen and Key biquads. Drawing 25/21mA from a 1.1V supply, an IIP3 of −13/−12dBV to −16.7/−18.3dBV and an input-referred noise of 320/280µVrms are measured for the 880/1760MHz filter.

On the relationship between the CMRR or PSRR and the second harmonic distortion of differential input amplifiers

The results of a harmonic distortion analysis for a differential pair are presented, including the effects of mismatches and of the finite nonlinear common-mode rejection ratio (CMRR) or power-supply rejection ratio (PSRR). Due to mismatches, a differential pair produces second-harmonic distortion. The presence of a finite common-mode gain limits the amount of feedback which can be usefully applied to suppress the harmonic distortion. When the common-mode gain is nonlinear, additional distortion is generated which is not suppressed by the feedback. When the amplifier has to drive a large load and when the supply line impedance is large, the finite PSRR causes similar effects. >

21.4 A 42mW 230fs-jitter sub-sampling 60GHz PLL in 40nm CMOS

For high data-rate communication at 60GHz using the IEEE 802.11ad standard, the LO synthesis needs both a low-noise VCO and low in-band phase noise. In the PLL shown in this paper, a QVCO with superharmonic passive coupling exhibits a large swing and low phase noise even with a 0.9V supply. In-band phase noise is reduced thanks to the use of a sub-sampling phase detector (SSPD), earlier introduced for low-GHz PLLs [1]. As most of the divider chain and the charge pump (CP) can be powered down in the sub-sampling mode, power consumption is also reduced.

Performance degradation of an LC-tank VCO by impact of digital switching noise

In mixed-signal designs, digital switching noise is an important limitation for the analog and RF performance. This paper reports a thorough experimental and analytical study of the impact of digital switching noise on a 3.5 GHz LC-tank voltage controlled oscillator (VCO) in 0.18 /spl mu/m CMOS. Frequency modulation is recognized as the dominating mechanism behind the impact of digital switching noise in the investigated frequency range (DC to 15 MHz). The dominating coupling path, from the source of noise to the VCO, in this frequency range is via the non-ideal metal ground lines.

Dataflow simulation of mixed-signal communication circuits using a local multirate, multicarrier signal representation

The explosion of the telecommunications market requires miniaturization and cost-effective realization of the front-ends of transceivers for digital telecommunications. New architectures must therefore be simulated at a high level. Current methodologies and corresponding tools suffer from common drawbacks, such as low accuracy, slow simulation speed, etc. A new methodology has been developed for efficient simulation of mixed-signal front-ends of digital telecom transceivers at the architectural level. Efficient execution is obtained using a multirate, multicarrier signal representation together with a dataflow simulation scheme that switches dynamically to the most efficient signal processing technique available. An implementation of this methodology shows both excellent runtimes and a high accuracy for realistic front-end architectures.