Ewout Martens

Classification of analog synthesis tools based on their architecture selection mechanisms

This overview paper presents a classification and brief descriptions of design strategies supported by analog EDA tools developed by researchers and companies in recent history over more than 20 years. In contrast to other classification systems, the method used to obtain the topology or architecture is taken as base for the classification. Different methods may be preferred depending on the type of system, the abstraction level, the experience of the designer or the need for extensive exploration of different architectures. Therefore, this overview helps the analog designer to select the right approach for the right task.

RF-to-Baseband Digitization in 40 nm CMOS With RF Bandpass

A fourth-order continuous-time RF bandpass ΔΣ ADC has been fabricated in 40 nm CMOS for fs/4 operation around a 2.22 GHz central frequency. A complete system has been implemented on the test chip including the ADC core, the fractional-N PLL with clock generation network, and the digital decimation filters and downconversion (DFD). The quantizers of the ADC are six times interleaved enabling a polyphase structure for the DFD and relaxing clock frequency requirements. This quantization scheme realizes a sampling rate of 8.88 GS/s which is the highest sampling speed for RF bandpass ΔΣ ADCs reported in standard CMOS to date enabling high oversampling ratios for RF digitization without compromising power-efficient implementation of the DFD. Measurements show that the ADC achieves a dynamic range of 48 dB in a band of 80 MHz with an IIP3 of 1 dBm.

\Delta\Sigma

Circuit-level simulation of /spl Delta//spl Sigma/ modulators is a time-consuming task, taking one or more days for meaningful results. While there are a great variety of techniques and tools that speed up the simulations for discrete-time /spl Delta//spl Sigma/ modulators, there is no rigorous methodology implemented in a tool to efficiently simulate and design the continuous-time counterpart. Nevertheless, in todays low-power, high-accuracy and/or very high-speed demands for A-to-D converters, designers are often forced to resort to the use of continuous-time /spl Delta//spl Sigma/ topologies. In this paper, we present a method for the high-level simulation of continuous-time /spl Delta//spl Sigma/ modulators as needed in top-down design and high-level modulator optimization. The method is based on analytical integration using behavioral models and exhibits the best tradeoff between accuracy, speed, and extensibility in comparison with other possible techniques that are reviewed briefly in this work. This methodology has been implemented in a user-friendly tool. Nonidealities such as finite gain, finite GBW, output impedance, and also nonlinearities, such as clipping, harmonic distortion, and the important effect of jitter are modeled. Finally, the tool was used to carry out some design-relevant experiments, illustrating the straightforward way of obtaining and exploring design tradeoffs at the modulator architectural level.

Modulator and Polyphase Decimation Filter

A software-defined radio receiver is presented, operating from 400 MHz to 6 GHz. The split front-end architecture has a low-band RF path (0.4-3 GHz) using 8-phase passive mixers and a high-band RF path (3-6 GHz) using 4-phase passive mixers. DC-offset, IIP 2, and harmonic recombination for harmonic rejection may be calibrated to achieve true wideband specifications. A 0.5-50 MHz tunable baseband bandwidth implies compliance with LTE and future standards. Despite having a 0.9 V supply, the receiver architecture ensures high out-of-band linearity. The 0.6 mm2, 28 nm CMOS receiver achieves down to 1.8 dB NF, >+3 dBm out-of-band IIP3, >70 dB calibrated HR3/5 and >+80 dBm calibrated IIP2. It tolerates 0 dBm blockers at 80 MHz offset with a blocker NF of 10 dB for a power consumption of 20-40 mW.

An analytical integration method for the simulation of continuous-time /spl Delta//spl Sigma/ modulators

In a generic behavioral model of an analog or mixed-signal electronic system, the internal and external signals and their interactions are formulated by more general descriptions than in commonly used behavioral models. This allows a more flexible design methodology. Whereas a behavioral model models an architecture of a system at a specific abstraction level, a generic behavioral model is built up out of generic functions that by specialization of these functions allows the modeling of a wide range of system architectures with different degrees of modeling accuracy. This enhanced abstraction level makes the approach suited for systematic analysis through refinement and architectural exploration of analog and mixed-signal building blocks and systems using computer-aided-design tools. As an application of this methodology, a generic behavioral model has been developed for continuous-time (CT) /spl Delta//spl Sigma/ analog-to-digital converters (ADCs) together with the specialization functions to take into account all major nonidealities at different levels of detail, including effects like jitter, saturation, and weakly nonlinear distortion. The results of experiments of a SystemC implementation of the model are presented. Compared to other models for analysis, the proposed method enables high accuracy even at low abstraction levels, whereas the event-driven character of the model results in short simulation times compared to time-marching simulations of behavioral models, written for example in very-high-speed-integrated-circuit (VHSIC) Hardware Description Language Analog and Mixed Signal (VHDL-AMS) or Matlab/Simulink. The flexibility of the model is demonstrated.

A 0.9 V 0.4–6 GHz Harmonic Recombination SDR Receiver in 28 nm CMOS With HR3/HR5 and IIP2 Calibration

Circuit--level simulation of ΔΣ modulators is a time--consuming task (taking one or more days for meaningful results). While there are a great variety of techniques and tools that speed up the simulations for discrete--time (DT) ΔΣ modulators, there is no rigorous methodology implemented in a tool to efficiently simulate and design the continuous--time (CT) counterpart. Yet, in todays low--power, high--accuracy and/or very high--speed demands for A--to--D converters, designers are often forced to resort to the use of CT ΔΣ topologies. In this paper, we present a method for the high--level simulation of continuous--time ΔΣ modulators that is based on behavioral models and which exhibits the best trade--off between accuracy, speed and extensibility compared to other possible techniques that are reviewed briefly in this work. A user--friendly tool, implementing this methodology, is then presented. Nonidealities such as finite gain, finite GBW, output impedance and also nonlinearities such as clipping, harmonic distortion and the important effect of jitter are modeled. Finally, experiments were carried out using the tool, exploring important design trade--offs.

Analyzing continuous-time /spl Delta//spl Sigma/ Modulators with generic behavioral models

A new approach for automated synthesis of analog and mixed-signal systems is presented. The heterogeneous genetic optimization strategy starts from a functional description and evolves a simple design solution in a strict top-down design process to a complex one that fulfills multiple objectives. Transformations of both architecture and parameters are applied. The expected improvement of the violated objectives is used as driver for the transformation selection. The topology is really created, giving the opportunity to explore new architectures

A behavioral simulation tool for continuous-time ΔΣ modulators

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Top-Down Heterogeneous Synthesis of Analog and Mixed-Signal Systems

An electrical-balance duplexer achieving the state-of-the-art linearity and insertion loss (IL) performance is presented, enabled by a partially depleted RF silicon-on-insulator CMOS technology. A single-ended configuration avoids the common-mode isolation problem suffered by topologies with a differential low-noise amplifier. Highly linear switched capacitors allow for impedance balancing to antennas with <;1.5:1 voltage standing wave ratio from 1.9 to 2.2 GHz. +70-dBm input-referred third-order intercept point is achieved under high transmitter (TX) power (+30.5 dBm max.). TX IL is <;3.7 dB, and receiver IL is <;3.9 dB.

High-Level Modeling and Synthesis of Analog Integrated Systems

Circuit-level simulation of /spl Delta//spl Sigma/ modulators is a time-consuming task (taking one or more days for meaningful results). While there are a great variety of techniques and tools that speed up the simulations for discrete-time (DT) /spl Delta//spl Sigma/ modulators, there is no rigorous methodology implemented in a tool to efficiently simulate and design the continuous-time (CT) counterpart. Yet, in todays low-power, high-accuracy and/or very high-speed demands for A-to-D converters, designers are often forced to resort to the use of CT /spl Delta//spl Sigma/ topologies. In this paper, we present a method for the high-level simulation of continuous-time /spl Delta//spl Sigma/ modulators that is based on behavioral models and which exhibits the best trade-off between accuracy, speed and extensibility compared to other possible techniques that are reviewed briefly in this work. A user-friendly tool, implementing this methodology, is then presented. Nonidealities such as finite gain, finite GBW, output impedance and also nonlinearities such as clipping, harmonic distortion and the important effect of jitter are modeled. Finally, experiments were carried out using the tool, exploring important design trade-offs.