Gerhard Knoblinger

Low-temperature electron mobility in Trigate SOI MOSFETs

Evidence of one-dimensional subband formation is found at low temperature in trigate silicon-on-insulator MOSFETs, resulting in oscillations of the I/sub D/(V/sub G/) characteristics. These oscillations correspond to the filling of energy subbands by electrons as the gate voltage is increased. High mobility, reaching 1200 cm/sup 2//Vs, is measured in the subbands at T=4.4 K. Subband mobility decreases as temperature is increased. Conduction in subbands disappears for temperatures higher than 100 K or for drain voltage values that are significantly larger than kT/q.

Temperature effects on trigate SOI MOSFETs

Trigate silicon-on-insulator (SOI) MOSFETs have been measured in the 5-400 K temperature range. The device fin width and height is 45 and 82 nm, respectively, and the p-type doping concentration in the channel is 6/spl times/10/sup 17/ cm/sup -3/. The subthreshold slope varies linearly with temperature as predicted by fully depleted SOI MOS theory. The mobility is phonon limited for temperatures larger than 100 K, while it is limited by surface roughness below that temperature. The corner effect, in which the device corners have a lower threshold voltage than the top and sidewall Si/SiO/sub 2/ interfaces, shows up at temperatures lower than 150 K.

Radiation Dose Effects in Trigate SOI MOS Transistors

N-channel trigate SOI MOSFETs have been irradiated with 60 Co gamma rays at doses up to 6 Mrad(SiO2). The threshold voltage shift at 6 Mrad is less than 10 mV in transistors with a gate length of 0.3 mum. At 6 Mrad(SiO2), the current drive reduction in the same devices is 10% if VG=0 V during irradiation and 20% if VG=1 V during the irradiation. The generation of positive charges in the BOX increases the electron concentration at the bottom interface of the silicon fins. Inversion electrons at the bottom interface have a higher mobility than the electrons at the (110)-oriented fin sidewalls. As a result, an increase of transconductance with dose is observed at moderate doses [<1 Mrad(SiO2)]. At higher doses, the usual mobility degradation caused by interface trap generation is observed

Design and evaluation of basic analog circuits in an emerging MuGFET technology

Multi-gate MOSFET (MuGFET) are the most promising candidates for beyond 45nm technology CMOS nodes. For future SoC solutions in these technologies the ability to realize also analog building blocks is of utmost importance. Up to now only a few publications are available concerning the perspective of FinFETs for analog applications and no reports and measurement results can be found about the realization of analog circuits with these advanced devices. In this work the design and realization of basic analog circuits (low voltage bandgap, Miller op amp and current reference) with FinFET devices were demonstrated for the first time, including measurement results.

Circuit design issues in multi-gate FET CMOS technologies

Multi-gate FETs are promising for sub-45nm CMOS technologies. To address the link between design and technology, basic digital and analog circuits are fabricated using FinFET and triple-gate FETs. Digital circuit performance, leakage currents, and power dissipation are characterized. The triple-gate FET achieves the lowest gate delay (27ps at 1.2V) and is >30% faster than FinFET with same oxide thickness of 2nm and gate lengths of 80nm. A FinFET-based Miller OpAmp achieves 45dB dc gain at 1.5V

A new model for thermal channel noise of deep submicron MOSFETs and its application in RF-CMOS design

In this paper we present a simple analytical model for the thermal channel noise of deep submicron MOS transistors including hot carrier effects. The model is verified by measurements and implemented in the standard BSIM3v3 SPICE model. We show that the consideration of this additional noise caused by hot carrier effects is essential for the correct simulation of the noise performance of a LNA in the GHz range.

Design of Ultra-Wideband Low-Noise Amplifiers in 45-nm CMOS Technology: Comparison Between Planar Bulk and SOI FinFET Devices

This paper deals with the design of single-stage differential low-noise amplifiers for ultra-wideband (UWB) applications, comparing state-of-the-art planar bulk and silicon-on-insulator (SOI) FinFET CMOS technologies featuring 45-nm gate length. To ensure a broadband input impedance matching, the g m-boosted topology has been chosen. Furthermore, the amplifiers have been designed to work over the whole UWB band (3.1-10.6 GHz), while driving a capacitive load, which is a realistic assumption for direct conversion receivers where the amplifier directly drives a mixer. The simulations (based on compact models obtained from preliminary measurements) highlight that, at the present stage of the technology development, the planar version of the circuit appears to outperform the FinFET one. The main reason is the superior cutoff frequency of planar devices in the inversion region, which allows the achievement of noise figure and voltage gain comparable to the FinFET counterpart, with a smaller power consumption.

Thermal channel noise of quarter and sub-quarter micron NMOSFET's

We present a simple and efficient method for the extraction of thermal channel noise of MOSFETs in quarter and sub-quarter micron technologies from NF50 (noise figure at 50 ohm source resistance) measurements. For shorter channel lengths the experimental results shows a continuously rising deviation from the classical long channel theory. For a 0.18 /spl mu/m technology a /spl phi//spl ap/6 instead of 2/3 in saturation was extracted (increase of factor 9 compared to the long channel theory).

RF-Noise of Deep-Submicron MOSFETs: Extraction and Modeling

A method for the extraction of all four noise parameters of a MOSFET (channel noise, induced gate noise and complex correlation coefficient) based on a description of noise by means of correlation matrices is presented. For the first time values for the gate noise and the correlation coefficient for deep-submicron transistors are reported. Compared to long channel theory an increase of the gate noise up to a factor 30 is observed.

Self Heating Simulation of Multi-Gate FETs

Due to material properties and geometric aspects self heating simulation of silicon devices requires 3D simulation of large structures. Fully coupled electrothermal simulation in three spatial dimensions is extremely memory and CPU time intensive. This work demonstrates a simplification of the approach to a thermal only problem from which much useful information can be extracted. We have applied this approach to a typical trigate device on SOI substrate. The simulated thermal resistance is in reasonable agreement with measurements. Parameters for the width dependent compact model for the thermal resistance can readily be extracted. The dependence of thermal resistance on the thickness of the bottom oxide has also been investigated. Moreover this permits transient behavior to be simulated in much more detail than is possible to be measured experimentally. Thus time constants and thermal capacitances for thermal compact models which are usually difficult to extract experimentally may be simulated numerically