Klaus Schruefer

The effects of fluorine on parametrics and reliability in a 0.18-/spl mu/m 3.5/6.8 nm dual gate oxide CMOS technology

Fluorine was introduced into the gate oxide by implantation at various doses into the gate polysilicon. After complete processing, the fluorine remaining in the system was characterized by secondary ion mass spectroscopy (SIMS) and then correlated to a number of important technological device parameters. The threshold voltages of thin (3.5 nm) and thick (6.8 nm) field-effect transistors (FETs) were measured, and an increase in interface trap density with increasing fluorine content was identified. An increase in oxide thickness and improvement in hot-carrier immunity were observed. Little change to oxide dielectric integrity was noted, but the negative bias threshold instability (NBTI) shift was improved with the introduction of fluorine. These data indicate that benefits may be obtained by introducing fluorine into the p-type FET (PFET), but that the increase in interface traps makes fluorine in the n-type FET (NFET) less attractive from a technological perspective. These data are in agreement with a previously proposed mechanism whereby fluorine removes hydrogen-related sites from the oxide.

A 0.13 /spl mu/m CMOS platform with Cu/low-k interconnects for system on chip applications

We describe an advanced 0.13 /spl mu/m CMOS technology platform optimized for density, performance, low power and analog/mixed signal applications. Up to 8 levels of copper interconnect with the industrys first true low-k dielectric (SiLK, k=2.7) (Goldblatt et al., 2000) result in superior interconnect performance at aggressive pitches. A 2.28 /spl mu/m/sup 2/ SRAM cell is manufactured with high yield by introducing elongated local interconnects on the contact level without increasing process complexity. Trench based embedded DRAM is offered for large area memory. Modular analog devices as well as passive components like resistors, MIM capacitors and intrinsic inductors are integrated.

Impact of strained-silicon-on-insulator (sSOI) substrate on FinFET mobility

In this letter, it is shown that for fin widths down to < 20 nm, strain can be retained in patterned strained-silicon-on-insulator (sSOI) films and is correlated to mobility enhancements observed in FinFET devices. NMOS FinFET mobility is improved by 60% and 30% for [110]/<110> and (100)/<100> fin surface/direction, respectively. Although PMOS FinFET mobility is degraded by 35% for [110]/<110> fins, it is enhanced by up to 30% for (100)/<100> fins. These results can be qualitatively explained using the bulk-Si piezoresistance coefficients.

Low-temperature electron mobility in Trigate SOI MOSFETs

Evidence of one-dimensional subband formation is found at low temperature in trigate silicon-on-insulator MOSFETs, resulting in oscillations of the I/sub D/(V/sub G/) characteristics. These oscillations correspond to the filling of energy subbands by electrons as the gate voltage is increased. High mobility, reaching 1200 cm/sup 2//Vs, is measured in the subbands at T=4.4 K. Subband mobility decreases as temperature is increased. Conduction in subbands disappears for temperatures higher than 100 K or for drain voltage values that are significantly larger than kT/q.

Temperature effects on trigate SOI MOSFETs

Trigate silicon-on-insulator (SOI) MOSFETs have been measured in the 5-400 K temperature range. The device fin width and height is 45 and 82 nm, respectively, and the p-type doping concentration in the channel is 6/spl times/10/sup 17/ cm/sup -3/. The subthreshold slope varies linearly with temperature as predicted by fully depleted SOI MOS theory. The mobility is phonon limited for temperatures larger than 100 K, while it is limited by surface roughness below that temperature. The corner effect, in which the device corners have a lower threshold voltage than the top and sidewall Si/SiO/sub 2/ interfaces, shows up at temperatures lower than 150 K.

Mechanism and process dependence of negative bias temperature instability (NBTI) for pMOSFETs with ultrathin gate dielectrics

This work mainly focuses on the NBTI (Negative Bias Temperature Instability) mechanism and investigates the degree of degradation caused by NBTI stress for different gate dielectrics, including thermally-grown and heavily-nitrided oxide films. The capability of our model has been demonstrated by excellent agreement between the fitted curves and experiments for ultrathin gate dielectrics (1.7 nm - 3.3 nm) fabricated by different processes. Among the various gate dielectrics under consideration, RPN (remote plasma nitrided oxide) is most resistant to NBTI stress.

Mechanism of Threshold Voltage Shift (ΔVth) Caused by Negative Bias Temperature Instability (NBTI) in Deep Submicron pMOSFETs

The physical mechanism responsible for negative bias temperature instability (NBTI), which is basic to the minimization of this degradation mode, is investigated, and an analytical model is developed accordingly. Experiments with 1.7 nm to 3.3 nm gate dielectrics fabricated by different processes demonstrate the capability of the proposed model.

Design and evaluation of basic analog circuits in an emerging MuGFET technology

Multi-gate MOSFET (MuGFET) are the most promising candidates for beyond 45nm technology CMOS nodes. For future SoC solutions in these technologies the ability to realize also analog building blocks is of utmost importance. Up to now only a few publications are available concerning the perspective of FinFETs for analog applications and no reports and measurement results can be found about the realization of analog circuits with these advanced devices. In this work the design and realization of basic analog circuits (low voltage bandgap, Miller op amp and current reference) with FinFET devices were demonstrated for the first time, including measurement results.

Circuit design issues in multi-gate FET CMOS technologies

Multi-gate FETs are promising for sub-45nm CMOS technologies. To address the link between design and technology, basic digital and analog circuits are fabricated using FinFET and triple-gate FETs. Digital circuit performance, leakage currents, and power dissipation are characterized. The triple-gate FET achieves the lowest gate delay (27ps at 1.2V) and is >30% faster than FinFET with same oxide thickness of 2nm and gate lengths of 80nm. A FinFET-based Miller OpAmp achieves 45dB dc gain at 1.5V

Retention characteristics of zero-capacitor RAM (Z-RAM) cell based on FinFET and tri-gate devices

In this paper we experimentally study for the first time the retention characteristics of Z-RAM cells based on CMOS FinFET and tri-gate devices. A retention time of few milliseconds is measured at room temperature on 100 nm devices. This FinFET based Z-RAM memory will allow manufacturing of very low cost DRAMs and eDRAMs for 45 and sub 45-nm generations.