Christian Pacha

Threshold logic circuit design of parallel adders using resonant tunneling devices

Resonant tunneling devices and circuit architectures based on monostable-bistable transition logic elements (MOBILEs) are promising candidates for future nanoscale integration. In this paper, the design of clocked MOBILE-type threshold logic gates and their application to arithmetic circuit components is investigated. The gates are composed of monolithically integrated resonant tunneling diodes and heterostructure field-effect transistors. Experimental results are presented for a programmable NAND/NOR gate. Design related aspects such as the impact of lateral device scaling on the circuit performance and a bit-level pipelined operation using a four phase clocking scheme are discussed. The increased computational functionality of threshold logic gates is exploited in two full adder designs having a minimal logic depth of two circuit stages. Due to the self-latching behavior the adder designs are ideally suited for an application in a bit-level pipelined ripple carry adder. To improve the speed a novel pipelined carry lookahead addition scheme for this logic family is proposed.

Manufacturability and robust design of nanoelectronic logic circuits based on resonant tunnelling diodes

The manufacturability of logic circuits based on quantum tunnelling devices, namely double-barrier resonant tunnelling diodes (RTD), is studied in detail. The homogeneity and reproducibility of III/V mesa technology-based devices is experimentally evaluated and interpreted using multiple I-V characteristic simulations. The experimental sensitivity of the RTD I-V parameters on well and barrier thickness is compared with multiple I-V simulations. With shrinking minimum feature size the fluctuations in the peak current can be directly attributed to an RTD area variation caused by the increasing impact of lithography and etching on lateral dimensions. These results prove that the III/V technology fulfils the requirements for a large scale integration of RTD devices. A nanoelectronic circuit architecture based on an improved MOBILE threshold logic gate is presented. Detailed SPICE simulations using the experimental data show that clock and supply voltage fluctuations are tolerated up to ± 0.1 V at a supply voltage of 0.7 V. Very strong local peak voltage variations of 15 per cent in opposite directions would be necessary to have a critical impact on to the circuit functionality. Smaller deviations only affect the timing without degrading the reliability of the circuit. Consequently, the design of a stable power supply and clocking scheme is more important for the overall circuit performance than the small relative deviations of the RTD peak voltage.

Efficiency of body biasing in 90-nm CMOS for low-power digital circuits

The efficiency of body biasing for leakage reduction and performance improvement in a 90-nm CMOS low-power technology with triple-well option is evaluated. Static measurements of single devices and dynamic measurements of ring oscillators and 32-b parallel prefix adders are presented. Whereas forward biasing still provides a significant performance improvement of up to 37% for low-leakage devices with 2.2-nm gate oxide thickness, the application of reverse biasing to reduce subthreshold leakage currents is inefficient due to additional leakage currents such as gate leakage and gate-induced drain leakage. Experimental results confirm that, in 90-nm CMOS circuits, the efficiency of body biasing strongly depends on the device type and operating temperature. Moreover, the impact of the zero-temperature coefficient point on static device and dynamic circuit performance is investigated.

Impact of STI-induced stress, inverse narrow width effect, and statistical V/sub TH/ variations on leakage currents in 120 nm CMOS

Leakage currents in 120 nm CMOS technology are dependent on STI-induced stress (STIS), inverse narrow-width effect (INWE), and statistical threshold voltage variations. In this paper, we analyze the impact of these effects on the gate-width dependence of the device off-current density. A threshold voltage model is proposed to describe the observed off-current minimum. STIS dominates the device behavior for large gate widths while INWE determines the off-current for gate widths below 1 /spl mu/m. Statistical threshold voltage variations are relevant for minimum-sized devices.

Circuit design issues in multi-gate FET CMOS technologies

Multi-gate FETs are promising for sub-45nm CMOS technologies. To address the link between design and technology, basic digital and analog circuits are fabricated using FinFET and triple-gate FETs. Digital circuit performance, leakage currents, and power dissipation are characterized. The triple-gate FET achieves the lowest gate delay (27ps at 1.2V) and is >30% faster than FinFET with same oxide thickness of 2nm and gate lengths of 80nm. A FinFET-based Miller OpAmp achieves 45dB dc gain at 1.5V

AC-only RF ID tags for barcode replacement

An RF ID concept using ac-powered circuits without DC conversion is demonstrated for barcode replacement. A 32b codeword ID tag including an RF front-end, voltage limiter, frequency divider, ROM and power modulator has a 0.02mm/sup 2/ area in a 0.13/spl mu/m CMOS process. A packaging technology uses a sidewall contact to facilitate the assembly process.

An Effective Switching Current Methodology to Predict the Performance of Complex Digital Circuits

A new methodology to assess dynamic circuit performance using basic device currents is presented. In contrast to existing effective drive current calculation considering inverters only, our approach provides precise circuit delays of product-relevant NAND and NOR logic gates over a wide range of supply voltages. The relevance of currents in the linear regime for circuit performance in sub-65 nm CMOS technologies is demonstrated also experimentally by a 65% performance boost in complex multi-gate FET circuits.

A 90-nm CMOS Low-Power GSM/EDGE Multimedia-Enhanced Baseband Processor With 380-MHz ARM926 Core and Mixed-Signal Extensions

To meet the widely varying speed and power requirements of multifunctional mobile devices, an appropriate combination of technology features, circuit-level low-power techniques, and system architecture is implemented in a GSM/Edge baseband processor with multimedia and mixed-signal extensions. Power reduction techniques and performance requirements are derived from an analysis of relevant use cases and applications. The 44 mm2 baseband processor is fabricated in a 90-nm low-power CMOS technology with triple-well option and dual-gate oxide core devices. The ARM926 core achieves a maximum clock frequency of 380 MHz at 1.4-V supply due to the usage of thin oxide (1.6 nm) devices. Power dissipation can be adapted to the performance requirements by means of combined voltage and frequency scaling to reduce active power consumption in medium-performance mode by 68%. To reduce leakage currents during standby mode, large SRAM blocks, nFET sleep transistors, and circuit components with relaxed performance requirements are implemented using devices with 2.2-nm gate oxide thickness

A threshold logic full adder based on resonant tunneling transistors

Resonant tunneling transistors and circuit architectures with enhanced computational functionality are promising candidates for future nano-scale integration. In this paper we propose a full adder cell based on multiple terminal linear threshold gates. The threshold gates are composed of monolithically integrated resonant tunneling diodes and heterostructure field effect transistors. Together with a bit-level pipelining scheme this leads to an efficient implementation with a minimal logic depth of two circuit layers.

Efficiency of body biasing in 90 nm CMOS for low power digital circuits

This paper presents an evaluation of body biasing, based on measured static and dynamic device performance. The efficiency of body biasing in sub-130 nm CMOS circuits strongly depends on the device type and operating temperature. While forward biasing still provides a significant performance gain in a 90 nm CMOS triple well process, the efficiency of reverse biasing nearly vanishes. The impact of the zero temperature coefficient point on low voltage digital circuit design is investigated.