Geun-il Lee

A 1.5-V 3.2 Gb/s/pin Graphic DDR4 SDRAM With Dual-Clock System, Four-Phase Input Strobing, and Low-Jitter Fully Analog DLL

Three circuit techniques for a 1.5 V, 512 Mb graphic DDR4 (GDDR4) SDRAM using a 90-nm DRAM process have been developed. First, a dual-clock system increases clocking accuracy and expands internal timing margins for harmonious core operation regardless of external clock frequency. Second, a four-phase data input strobe scheme helps to increase the input data valid window. Third, a fully analog delay-locked loop which provides a stable I/O clock and has 31.67 ps peak-to-peak jitter characteristics is designed. On the basis of these circuit techniques, the data rate is 3.2 Gbps/pin, which corresponds to 12.8 Gbps in times32 GDDR4-based I/O. Also, a multidivided architecture consisting of four independent 128 Mb core arrays is designed to reduce power line and output noise.

A hierarchy bitline boost scheme for sub-1.5 V operation and short precharge time on high density FeRAM

This work develops three concepts: low-voltage operation with boost voltage control of bitline and plateline, reduced bitline capacitance with multiple divided sub cell array, and increased chip performance with write operation sharing both active and precharge time period. A 256 kb test chip with 3.0/spl times/1.0 /spl mu/m/sup 2/ 1T1C memory cells in 0.25 /spl mu/m design roles is expected to achieve 180 ns access and 70 ns precharge at 1.5 V based on internal probing.

Effect of Liner Oxide Densification on Stress-Induced Leakage Current Characteristics in Shallow Trench Isolation Processing

Controlling mechanical stress in the shallow trench isolation (STI) process is an increasing concern because it can affect circuit performance and yield. This paper presents the effect of liner oxide densification on the stress-induced junction leakage current in the STI process, compared to high density plasma (HDP) oxide densification before STI planarization. The simulation was performed for the trench isolation structure. It indicated that high temperature densification of the trench-tilled HDP oxide has a high probability of generating STI dislocations due to its inherently large mechanical stress and volume. The crystal defects and the mechanical stresses were significantly reduced by the introduction of liner oxide densification during STI processing; as a result, in the stress-induced junction, leakage characteristics were improved. The characteristics of standby current and column bit failure with regard to device yields have also been discussed.

A pulse-tuned charge controlling scheme for uniform main and reference bitline voltage generation on ITIC FeRAM

In order to improve cell array efficiency and reference voltage characteristics of ITlC FeRAM, two key techniques are proposed in this paper. 1) Cell operation scheme with pulse-tuned signals on wordline and plateline for achieving uniform bitline levels in short time and 2) reference voltage generation scheme using dual pulse control for reference voltage to track variable bitline sensing voltage in wide range of operation voltage and temperature. 2Mb ITlC FeRAM in unit block of 512 rows by 256 columns cell array with 0.35pm design rule are implemented. The optimized uniform bitline sensing voltage and reference voltage are achieved at the condition of the first wordline pulse signal of 3011s and the reference dual pulse signal time of 30-4011s at 3V in room temperature.