Jinyong Chung

CMOS charge pumps using cross-coupled charge transfer switches with improved voltage pumping gain and low gate-oxide stress for low-voltage memory circuits

To overcome the problems of the modified Dickson pump like NCP-2, a new pump (CCTS-1) where simple voltage doublers are cascaded in series and each of them has cross-coupled configuration is studied in this paper for possible use in low-voltage EEPROMs and DRAMs. Though this concept of cascading doublers has been previously proposed, it is firstly addressed in this paper that CCTS-1 has the lower gate-oxide stress, the improved voltage pumping gain, and the better power efficiency than NCP-2 so that CCTS-1 can be more suitable for the multi-stage pump in particular at low V/sub CC/. In addition, CCTS-2 is proposed to overcome the degraded body-effect of CCTS-1 without using boosted clocks when the stage number is large.

A 66-333-MHz 12-mW register-controlled DLL with a single delay line and adaptive-duty-cycle clock dividers for production DDR SDRAMs

The conventional register-controlled delay locked loop (RCDLL) with a single delay line requires a complex logic circuit following the phase comparator to prevent the false lock. A RCDLL with two delay lines was published to reduce the chip area and power consumption by comparing the frequency-divided slow signals. Further reductions of 20% in both chip area and power consumptions were achieved in the RCDLL proposed in this work by using a single delay line. The duty cycle of the clock divider output was adaptively changed between 25% and 50% according to the external clock frequency to minimize the number of delay elements and hence the jitter of DLL output clock. The adaptive-change of duty cycle reduced the peak-to-peak jitter of data output from 800 ps to 400 ps at the data rate of 266 Mb/s in the production 256-Mb DDR SDRAM. The worst-case power consumption and the chip size of the RCDLL chip fabricated by using a 0.15-/spl mu/m CMOS technology were measured to be 12-mW and 0.16-mm/sup 2/, respectively, at the data rate of 400 Mb/s and the supply voltage of 2.5 V.

An antifuse EPROM circuitry scheme for field-programmable repair in DRAM

An antifuse EPROM and 3-V programming circuit has been demonstrated in an existing 0.22-/spl mu/m DRAM process technology and is fully compatible with 64-Mb SDRAM specifications. The antifuse circuitry uses an internal high-voltage generator for programming and a dynamic sense and static latch scheme that appropriately enables redundant DRAM address decoders at power-up. For efficient high voltage generation, a high-voltage-tolerant capacitor structure was formed by using the high fringing capacitance available between intralevel and interlevel polysilicon and metal lines. Furthermore, the programmable EPROM element was realized without any process modifications by utilizing destructive dielectric breakdown of the thin, highly reliable oxide-nitride-oxide (ONO) dielectric in the basic DRAM cell capacitor structure. This antifuse EPROM circuit enables implementation of field-programmable DRAM features such as memory repair, output impedance matching, and data encryption.

A low-jitter wide-range skew-calibrated dual-loop DLL using antifuse circuitry for high-speed DRAM

This paper describes a delay-locked loop (DLL) circuit having two advancements, a dual-loop operation for a wide lock range and programmable replica delays using antifuse circuitry and internal voltage generator for a post-package skew calibration. The dual-loop operation uses information from the initial time difference between reference clock and internal clock to select one of the differential internal loops. This increases the lock range of the DLL to the lower frequency. In addition, incorporation of the programmable replica delay using antifuse circuitry and the internal voltage generator allows for the elimination of skews between external clock and internal clock that occur from on-chip and off-chip variations after the package process. The proposed DLL, fabricated on 0.16-/spl mu/m DRAM process, operates over the wide range of 42-400 MHz with 2.3-V power supply. The measured results show 43-ps peak-to-peak jitter and 4.71-ps rms jitter consuming 52 mW at 400 MHz.

Antifuse EPROM circuit for field programmable DRAM

A 3 V EPROM circuit is implemented in an existing 0.22 /spl mu/m DRAM process with an antifuse based on destructive breakdown of the highly-reliable 6.5 nm oxide-nitride-oxide (ONO) storage capacitor dielectric. Using an internal high-voltage charge pump, this antifuse EPROM is programmed without external high-voltage power supplies which facilitates full pin compatibility with existing SDRAM specifications. This antifuse EPROM circuit enables field programmable DRAM functionality such as post-package memory repair, output impedance matching for system memory module calibration, user programmable memory bank architectures, data encryption, and product serial numbers. While laser programmable polysilicon fuses are used extensively to provide nonvolatile memory for repair of defective DRAM cells, they are limited to programming at wafer level and before packaging. Previous implementations of antifuse EPROM utilized external high-voltage supplies for wafer level programming only due to the incompatibility of high voltage power supplies with existing DRAM pin configurations.

A fast pump-down V/sub BB/ generator for sub-1.5-V DRAMs

Based on the study about the previously developed V/sub BB/ generators, a fast pump-down and high-efficiency V/sub BB/ generator with a cross-coupled hybrid pumping circuit 2 (CHPC2) is presented in this paper. CHPC2 takes only the advantages from the previous generators, eliminating the disadvantages. CHPC2 shows a |V/sub BB/|/V/sub CC/ as large as 98% even at low V/sub CC/=0.9 V, strongly ensuring that it is suitable at sub-1.5-V DRAM applications. Moreover, CHPC2 exhibits a better pumping efficiency and a larger pumping current over the previous ones with a wide range of the load resistance at V/sub CC/=1.2 V.

A post-package bit-repair scheme using static latches with bipolar-voltage programmable antifuse circuit for high-density DRAMs

The antifuse programming voltages are changed into bipolar voltages of V/sub CC/ and -V/sub CC/, alleviating high-voltage problems such as permanent device breakdown and achieving a smaller layout area for the antifuse circuit than the previous scheme. In addition, an efficient bit-repair scheme is used instead of the conventional line-repair one, reducing a layout area for the redundancy bits. Using the static latches instead of the dynamic memory cells for the redundancy bits eliminates possible defects in the redundancy area, making this bit-repair scheme robust. The yield improvement using the post-package repair reaches as much as 3% for 0.16 /spl mu/m 256 M SDRAM.

Study of Organic Thin-Film Transistors Under Electrostatic Discharge Stresses

Low-voltage pentacene-based organic thin-film transistors (OTFTs) are characterized for the first time under the electrostatic discharge (ESD) stresses. The measurements are conducted using the transmission line pulsing (TLP) tester which generates the human body model equivalent pulses. The ESD behaviors and tolerances of OTFTs having different dimensions and gate biasing conditions are investigated. OTFTs failure mechanism and dc performance degradation due to the ESD stresses are also studied.

An offset cancellation bit-line sensing scheme for low-voltage DRAM applications

Offset-cancellation provides low-voltage DRAM operation. The offset cancelling bit-line sense amplifiers are pitch-matched to the conventional 0.16 /spl mu/m DRAM cell array without process modifications. Results indicate better refresh characteristics than conventional bit-line sense amplifiers even at 1.5 V.

Investigation of Sub-10-nm Diameter, Gate-All-Around Nanowire Field-Effect Transistors for Electrostatic Discharge Applications

Electrostatic discharge (ESD) robustness of a promising nanoscaled device, the gate-all-around nanowire field-effect transistor (NW FET), was characterized for the first time using the transmission-line pulsing technique. The effects of gate length, nanowire dimension, and nanowire count on the failure current, leakage current, trigger voltage, and on-resistance were investigated. ESD performances of the gate-all-around NW FET and other nanostructure devices, such as the poly-Si nanowire thin-film transistor and FinFET were also compared and discussed.