Seaung-Suk Lee

Modeling of

A threshold-voltage (Vth) shift of sub-100-nm NAND flash-memory cell transistors was modeled systematically, and the modeling was verified by comparing with the data from measurement and 3-D device simulation. The Vth shift of the NAND flash-memory cell was investigated by changing parameters such as gate length, width, drain voltage, dielectric material between cells, space between cells, lightly doped-drain depth, and adjacent-cell bias. The proposed model covers two dominant device physics: capacitance coupling effect between adjacent cells and short-channel effect. Our model showed an accurate prediction of the Vth shift of NAND flash-memory array and a good agreement with the data from simulation and measurement.

V_{\rm th}

We investigated the retention characteristics of (Bi,La)4Ti3O12 (BLT) capacitors and their lateral size effects in a fully integrated device structure. Unlike the commonly used Pb(Zr,Ti)O3 capacitors for ferroelectric random access memories (FeRAMs), which have poor opposite-state retention characteristics, BLT capacitors showed very stable characteristics in both the same- and the opposite-state retention tests. These good retention properties were closely related to the small amount of imprint in the BLT capacitors. In addition, the retention characteristics of BLT capacitors showed no practical degradation due to the size reduction, down to 0.49×0.64μm2, which could be used for highly integrated FeRAMs of 32MB density.

Shift in nand Flash-Memory Cell Device Considering Crosstalk and Short-Channel Effects

The imprint characteristics of SrBi2Ta2O9 (SBT) and Bi4-xLaxTi3O12 (BLT) thin films have been studied at elevated storage and operation temperatures for the application to ferroelectric random access memories (FeRAMs). After the storage at 125°C, a significant charge shift occurs as a function of the logarithmic time due to the thermally induced voltage shift. At an elevated operation temperature, the voltage shift divided by coercive voltage increases leading to the enhanced imprint degradation of polarization. Since the BLT thin film has larger remanent polarization and smaller voltage shift divided by coercive voltage at an elevated temperature than the SBT thin film, it has higher imprint endurance. In order to investigate the imprint characteristics on a device level, the sensing margin of the FeRAM cells using 0.8 µm complementary metal-oxide-semiconductor (CMOS) technology with SBT and BLT capacitors is also detected.

Retention properties of fully integrated (Bi,La)4Ti3O12 capacitors and their lateral size effects

This work develops three concepts: low-voltage operation with boost voltage control of bitline and plateline, reduced bitline capacitance with multiple divided sub cell array, and increased chip performance with write operation sharing both active and precharge time period. A 256 kb test chip with 3.0/spl times/1.0 /spl mu/m/sup 2/ 1T1C memory cells in 0.25 /spl mu/m design roles is expected to achieve 180 ns access and 70 ns precharge at 1.5 V based on internal probing.

Imprint Characteristics of Ferroelectric Thin Films at Elevated Storage and Operation Temperatures.

In this study, physical properties of different trapping nitrides were extracted, and the program efficiency of MANOS cell was explained. We also showed shallow traps were generated at trapping nitride by etching damage, and this could be cured resulting great improvement of cell performance. Lastly, erasure mechanism of TiN-gate MANOS cell was discussed with some experimental and modeling results.

A hierarchy bitline boost scheme for sub-1.5 V operation and short precharge time on high density FeRAM

We discuss some technical issues on the realization of high-density ferroelectric random access memory (FeRAM). Due to reliability concerns of ferroelectric materials, such as fatigue, retention, and imprint, an extra sensing margin is required. In order to overcome these drawbacks, we have improved the ferroelectric capacitor process and design architecture. The fatigue and imprint degradations of the ferroelectric capacitor are significantly suppressed using the newly developed (Bi1-xLax)4Ti3O12 (BLT) films. The design architecture was improved using the split word line (SWL) cell array and current gain cell (CGC) operation. Using the above BLT capacitors and design architectures, we have obtained a high sensing margin, a high cell efficiency, and a small cross-talk noise in high-density FeRAMs.

Modeling and Characterization of Program / Erasure Speed and Retention of TiN-gate MANOS (Si-Oxide-SiNx-Al2O3-Metal Gate) Cells for NAND Flash Memory

The imprint characteristics of SrBi2Ta2O9, SBT, and (Bi0.8La0.2)4Ti3O12, BLT, thin film capacitors have been evaluated at the storage temperature of 125 □. The coercive voltage shift and the polarization loss occurred as a function of the logarithmic storage time. BLT capacitors showed more stable imprint characteristics than SBT. The increasing rate of the coercive voltage shift and the decreasing rate of the polarization loss of BLT with a storage time were smaller than that of SBT. The BL sensing signals were measured on 2T2C-256 Kbits FeRAM adopted SBT and BLT capacitor in order to estimate the imprint life times of the devices, respectively.

Issues and Reliability of High-Density FeRAMs

Ramping amplitude multi-frequency charge pumping technique is proposed to analyze the nitride traps in silicon?oxide?nitride?oxide?silicon (SONOS) structure. Based on the method, the trap density and the capture cross section at each location in oxide?nitride?oxide (ONO) gate stack can be extracted separately. The trap parameters extracted from the suggested model show that the traps located at tunnel-oxide/nitride interface whose capture cross section is lowest. The cause of large trap density at tunnel-oxide/nitride interface may be due to Si?Si bonding formation as reported in previous works.

Imprint Characteristics of Bi-Layered Perovskite Ferroelectric Thin Films

The proposed current-gain scheme provides a key technical solution for a high density, low cost and high performance ferroelectric random access memory. The proposed sensing scheme shows maximum sensing-signal window because of divided sub-bitline (SBL) structure. The unit cell array section is composed of the cell array of 64 rows and 128 columns with SBL, SBL switch (SBSW) devices and current-gain transistor (CGT) device. The global main bitline (MBL) is biased by MBL sensing load (MSL) device and connected to common MBL bus (CMB) through block selection switch (BSS) device. The device sizes of CGT and MSL devices are key factors for determining the transfer characteristics of SBL and MBL. The 128 sense amplifiers in peripheral circuit region are shared to all cell array blocks through CMB with 128 MBL columns of each cell array block. The address access time of the 16 Mb chip is evaluated to less than 70 ns at 3 V.

New Charge Pumping Method for Characterization of Charge Trapping Layer in Oxide?Nitride?Oxide Structure

16M FeRAM was successfully developed using a (Bi1 − X La X )4Ti3O12, BLT, film with excellent imprint characteristic as a ferroelectric film to decrease capacitor size, current gain cell operation (CGCO) sensing scheme, and split word line (SWL) cell array architecture with hierarchical-double bit line in order to increase cell array efficiency. The chip size of 16M FeRAM could be reduced down to about 63% compared with a conventional one by the adoption of the novel ferroelectric material and the design architectures. The read/write access time and cycle time are 70 ns and 100 ns in operation voltage of 3.0 at room temperature, respectively. The operation and standby current are less than 20 mA and 10 μA, respectively.