Giampiero Montagna

Solutions for image rejection CMOS LNA

This paper deals with the realization of a high image rejection (IR) CMOS LNA, tailored to DECT applications. Two topologies are proposed. The first one makes use of a Q-enhancement circuit and provides 15 dB IR with 300 MHz IF, 4.5 dB NF and -13 dBm IIP3. A notch filter loads the second LNA. The results are the following: 30 dB IR, 5.5 dB NF and -10 dBm IIP3. In both cases the frequency control is performed by means of an integrated MOS varactor. These circuits prove to be suitable for highly integrated CMOS receivers employing wideband IF architecture. At the expense of an almost double current consumption with respect to classical LNA, they provide enough image rejection to get rid of off-chip image rejection filters.

A 72mW CMOS 802.11a direct conversion receiver with 3.5dB NF and 200kHz 1/f noise corner

A direct conversion 802.11a receiver front-end including a synthesizer with quadrature VCO has been integrated in a 0.13 /spl mu/m CMOS process. The chip has an active area of 1.8mm/sup 2/ with the entire RF portion operated from 1.2V and the low frequency portion operated from 2.5V. Its key feature is a current driven passive mixer with a low impedance load that achieves a low 1/f noise corner. Measured noise figure is 3.5dB with a 1/f noise corner at 200kHz, and an IIP3 of -2dBm. The synthesizer DSB phase noise integrated over a 10MHz band is less than -36dBc. The front end reported here has one of the lowest power consumption and 1/f noise corner at 5GHz in pure CMOS ever reported so far.

A 35-mW 3.6-mm^2 fully integrated 0.18- mu;m CMOS GPS radio

A single-chip CMOS Global Positioning System (GPS) radio has been integrated using only a couple of external passive components for the input matching network and one external reference for the synthesizer. The receiver downconverts the GPS L1 signal at 1575.42 MHz to an IF of 9.45 MHz. The complete front-end and frequency synthesizer section have been integrated: low noise amplifier, image rejection mixer, IF active filter, and the full phase-locked loop synthesizer, including voltage-controlled oscillator and loop filter. The front-end measured performances are 81-dB maximum gain, 5.3-dB noise figure, and >30-dB image rejection. The synthesizer features a phase noise of -95 dBc/Hz at 1-MHz offset and a total integrated phase noise of less than 7/spl deg/ rms in the 500-Hz-1.5-MHz band. The front-end and the synthesizer draw, respectively, 11 and 9 mA from a 1.8-V supply. The architecture of the front-end and synthesizer has been geared to high level of integration and reduction of silicon area at the lowest possible power consumption. Consequently, the one reported here is the smallest and most integrated CMOS GPS receiver reported so far.

A 35-mW 3.6-mm/spl 2/ fully integrated 0.18-μm CMOS GPS radio

A single-chip CMOS Global Positioning System (GPS) radio has been integrated using only a couple of external passive components for the input matching network and one external reference for the synthesizer. The receiver downconverts the GPS L1 signal at 1575.42 MHz to an IF of 9.45 MHz. The complete front-end and frequency synthesizer section have been integrated: low noise amplifier, image rejection mixer, IF active filter, and the full phase-locked loop synthesizer, including voltage-controlled oscillator and loop filter. The front-end measured performances are 81-dB maximum gain, 5.3-dB noise figure, and >30-dB image rejection. The synthesizer features a phase noise of -95 dBc/Hz at 1-MHz offset and a total integrated phase noise of less than 7/spl deg/ rms in the 500-Hz-1.5-MHz band. The front-end and the synthesizer draw, respectively, 11 and 9 mA from a 1.8-V supply. The architecture of the front-end and synthesizer has been geared to high level of integration and reduction of silicon area at the lowest possible power consumption. Consequently, the one reported here is the smallest and most integrated CMOS GPS receiver reported so far.

An 8 mA, 3.8 dB NF, 40 dB gain CMOS front-end for GPS applications

A fully differential 0.35μm CMOS LNA plus mixer, tailored to a double conversion architecture, for GPS applications has been realized. The LNA makes use of an inductively degenerated input stage and a resonant LC load, featuring 12% frequency tuning, accomplished by an MOS varactor. The mixer is a Gilbert cell like, in which an NMOS and a PMOS differential pair, shunted together, realize the input stage. This topology allows to save power, for given mixer gain and linearity. The front-end measured performances are: 40dB gain, 3.8dB NF, -25.5dBm IIP3, 1.3GHz input frequency, 140MHz output frequency, with 8mA from a 2.8V voltage supply.

A 35-mW 3.6-mm/sup 2/ fully integrated 0.18-/spl mu/m CMOS GPS radio

A single-chip CMOS Global Positioning System (GPS) radio has been integrated using only a couple of external passive components for the input matching network and one external reference for the synthesizer. The receiver downconverts the GPS L1 signal at 1575.42 MHz to an IF of 9.45 MHz. The complete front-end and frequency synthesizer section have been integrated: low noise amplifier, image rejection mixer, IF active filter, and the full phase-locked loop synthesizer, including voltage-controlled oscillator and loop filter. The front-end measured performances are 81-dB maximum gain, 5.3-dB noise figure, and >30-dB image rejection. The synthesizer features a phase noise of -95 dBc/Hz at 1-MHz offset and a total integrated phase noise of less than 7/spl deg/ rms in the 500-Hz-1.5-MHz band. The front-end and the synthesizer draw, respectively, 11 and 9 mA from a 1.8-V supply. The architecture of the front-end and synthesizer has been geared to high level of integration and reduction of silicon area at the lowest possible power consumption. Consequently, the one reported here is the smallest and most integrated CMOS GPS receiver reported so far.