Giuseppe Gramegna

A sub-1-dB NF/spl plusmn/2.3-kV ESD-protected 900-MHz CMOS LNA

A sub-1-dB noise figure HBM ESD-protected [-3 kV, 2.3 kV] low noise amplifier (LNA) has been integrated in a 0.35-/spl mu/m RF CMOS process with on-chip inductors. The sensitivity of the LNA performances to the spread of parasitics associated with package and bondwire has been attenuated by using an inductive on-chip source degeneration. At 920 MHz and P/sub dc/=8.6 mW, the LNA features: noise figure NF=1 dB, input return loss=-8.5 dB, output return loss=-27 dB, power gain G/sub p/=13 dB, input IIP3=-1.5 dBm. At a power dissipation of 5 mW and 17.6 mW, a NF respectively equal to 1.2 dB and 0.85 dB is measured. The CMOS LNA takes 12 pins of a TQFP48 package, an area of 1.0/spl times/0.66 mm/sup 2/ (bondwire pads excluded) and it is the first HBM ESD-protected [-3 kV, 2.3 kV] CMOS LNA to break the 1-dB NF barrier.

A 56-mW 23-mm/sup 2/ single-chip 180-nm CMOS GPS receiver with 27.2-mW 4.1-mm/sup 2/ radio

A 56-mW 23-mm/sup 2/ GPS receiver with CPU-DSP-64 kRAM-256 kROM and a 27.2-mW 4.1-mm/sup 2/ radio has been integrated in a 180-nm CMOS process. The SoC GPS receiver, connected to an active antenna, provides latitude, longitude, height with 3-m rms precision with no need of external host processor in a [-40, 105]/spl deg/C temperature range. The radio draws 17 mA from a 1.6-1.8-V voltage supply, takes 11 pins of a VFQFPN68 package, and needs just a few passives for input match and a crystal for the reference oscillator. Measured radio performances are NF=4.8 dB, Gp=92 dB, image rejection > 30 dB, -112 dBc/Hz phase noise @ 1 MHz offset from carrier. Though GPS radio linearity and ruggedness have been made compatible with the co-existence of a microprocessor, radio silicon area and power consumption is comparable to state-of-the-art stand-alone GPS radio. The one reported here is the first ever single-chip GPS receiver requiring no external host to achieve satellite tracking and position fix with a total die area of 23 mm/sup 2/ and 56-mW power consumption.

A 35-mW 3.6-mm^2 fully integrated 0.18- mu;m CMOS GPS radio

A single-chip CMOS Global Positioning System (GPS) radio has been integrated using only a couple of external passive components for the input matching network and one external reference for the synthesizer. The receiver downconverts the GPS L1 signal at 1575.42 MHz to an IF of 9.45 MHz. The complete front-end and frequency synthesizer section have been integrated: low noise amplifier, image rejection mixer, IF active filter, and the full phase-locked loop synthesizer, including voltage-controlled oscillator and loop filter. The front-end measured performances are 81-dB maximum gain, 5.3-dB noise figure, and >30-dB image rejection. The synthesizer features a phase noise of -95 dBc/Hz at 1-MHz offset and a total integrated phase noise of less than 7/spl deg/ rms in the 500-Hz-1.5-MHz band. The front-end and the synthesizer draw, respectively, 11 and 9 mA from a 1.8-V supply. The architecture of the front-end and synthesizer has been geared to high level of integration and reduction of silicon area at the lowest possible power consumption. Consequently, the one reported here is the smallest and most integrated CMOS GPS receiver reported so far.

A 35-mW 3.6-mm/spl 2/ fully integrated 0.18-μm CMOS GPS radio

A single-chip CMOS Global Positioning System (GPS) radio has been integrated using only a couple of external passive components for the input matching network and one external reference for the synthesizer. The receiver downconverts the GPS L1 signal at 1575.42 MHz to an IF of 9.45 MHz. The complete front-end and frequency synthesizer section have been integrated: low noise amplifier, image rejection mixer, IF active filter, and the full phase-locked loop synthesizer, including voltage-controlled oscillator and loop filter. The front-end measured performances are 81-dB maximum gain, 5.3-dB noise figure, and >30-dB image rejection. The synthesizer features a phase noise of -95 dBc/Hz at 1-MHz offset and a total integrated phase noise of less than 7/spl deg/ rms in the 500-Hz-1.5-MHz band. The front-end and the synthesizer draw, respectively, 11 and 9 mA from a 1.8-V supply. The architecture of the front-end and synthesizer has been geared to high level of integration and reduction of silicon area at the lowest possible power consumption. Consequently, the one reported here is the smallest and most integrated CMOS GPS receiver reported so far.

A 35-mW 3.6-mm/sup 2/ fully integrated 0.18-/spl mu/m CMOS GPS radio

A single-chip CMOS Global Positioning System (GPS) radio has been integrated using only a couple of external passive components for the input matching network and one external reference for the synthesizer. The receiver downconverts the GPS L1 signal at 1575.42 MHz to an IF of 9.45 MHz. The complete front-end and frequency synthesizer section have been integrated: low noise amplifier, image rejection mixer, IF active filter, and the full phase-locked loop synthesizer, including voltage-controlled oscillator and loop filter. The front-end measured performances are 81-dB maximum gain, 5.3-dB noise figure, and >30-dB image rejection. The synthesizer features a phase noise of -95 dBc/Hz at 1-MHz offset and a total integrated phase noise of less than 7/spl deg/ rms in the 500-Hz-1.5-MHz band. The front-end and the synthesizer draw, respectively, 11 and 9 mA from a 1.8-V supply. The architecture of the front-end and synthesizer has been geared to high level of integration and reduction of silicon area at the lowest possible power consumption. Consequently, the one reported here is the smallest and most integrated CMOS GPS receiver reported so far.

23mm/sup 2/ single-chip 0.18/spl mu/m CMOS GPS receiver with 28mW-4.1 mm/sup 2/ radio and CPU/DSP/RAM/ROM

A 23 mm/sup 2/ 0.18 /spl mu/m CMOS GPS receiver with ARM7-DSP-64 k RAM-256 k ROM and a 28 mW-4.1 mm/sup 2/ radio has been integrated. The SoC GPS receiver, connected to an active antenna, provides latitude, longitude, height with 3 m rms precision with no need of external host processor in [-20,80]/spl deg/C temperature range. The radio draws 17.5 mA from a 1.6 V-1.8 V supply, takes 11 pins of a VFQFPN68 package and needs just a few passives for input matching and one crystal. Measured radio performances are: NF=4.8 dB, Gp=92 dB, image rejection >30 dB, -112 dBc/Hz @ 1 MHz offset phase noise. Though linearity and ruggedness of the GPS radio have been made compatible with the co-existence of microprocessor, its silicon area and power consumption is aligned with state-of-the-art stand-alone CMOS GPS radio. The one reported here is the first ever radio successfully embedded into a single-chip GPS receiver requiring no external host to achieve satellite tracking and position fix with a total die area of 23 mm/sup 2/.