Gianluca Colli

B/W adaptive image grabber with analog motion vector estimator at 0.3 GOPS

The chip contains a B/W CMOS adaptive video-camera providing quarter common interface format (176/spl times/144 pels), two analog memories, a motion estimator (ME), and a small controller to synchronize computational phases. A modified scheme uses the two analog memories to compare consecutive frames. Good speed and power performance is obtained with only 0.5 dB loss in S/N ratio. A H261-compatible bit stream can be produced to interface with H261 decoders.

A 100-MHz 4-mW four-quadrant BiCMOS analog multiplier

A four-quadrant analog multiplier based on a simple, very linear, and fast BiCMOS transconductor using MOS transistors operating in the triode region and NPN bipolar devices is presented. The four quadrant operation is obtained by crosscoupling-in a Gilbert-cell fashion-two transconductors with a third stage used to modulate the transconductances of the former two. A chip prototype of the multiplier has been integrated in a 1.2-/spl mu/m BiCMOS process to validate the idea. It has been designed to achieve high linearity on both inputs: measured results show a total harmonic distortion (THD) of less than -40 dB with a 3-V peak-to-peak input signal at 5 MHz from a 5-V supply and an output -3 dB bandwidth of 100 MHz while dissipating 4 mW from a 3-V supply. The integrated chip prototype active area is 1 mm/sup 2/.

Low power, low voltage conductance-mode CMOS analog neuron

Analog implementations of neural networks have been used for a wide variety of tasks especially in the area of image processing. Typically, implementations of analog neural networks have been based on the use of either current or charge as the variable of computation. This work introduces a new class of analog neural network circuits based on the concept of conductance-mode computation. In this class of circuits, accumulated weighted inputs are represented as conductances, and a conductance-mode neuron is used to apply nonlinearity and produce an output. The advantages of this class of circuits are twofold: firstly, conductance-mode computation is fast-we have developed circuits based on these principles which compute at 5-10 MHz; secondly, because conductance-mode computation requires the minimum charge necessary to compare two conductances, its energy-consumption is self-scaling depending on the difficulty of the decision to be made-we have a working prototype which consumes 166 fJ per connection. The computing precision of these circuits is high: test results on a small test structure indicate an intrinsic precision of 8-9 bits. We have developed a larger test circuit which is able to perform computation with 1056 binary-valued inputs. Initial measurements in this large test structure indicate a more limited computing precision of 6+ to 8+ bits depending on the common mode of the input signal.

An analog memory for a QCIF format image frame storage

An analog memory suitable for storage of a photogenerated image frame is described. An architecture that allows a fast writing rate is presented. The memory has a serial input and eight channels parallel output; it can store a QCIF image (176/spl times/144 pixels) for 1/15 sec with an equivalent precision of 7 bit. Nominal input writing frequency is 2.5 MHz and output reading frequency is 0.833 MHz. The chip needs an external reference clock at 2.5 MHz. The single cell size is 22/spl times/21.2 /spl mu/m. The consumption power of the chip is 6 mW@5 Volts power supply. It has been made using a 0.7 /spl mu/m CMOS technology supplied by SGS-Thomson.