Ernestina Chioffi

High-speed, low-switching noise CMOS memory data output buffer

This paper describes a data output buffer for highspeed CMOS integrated memories with a high data output pin count. The buffer minimizes the switching noise induced on supply lines while achieving very fast output transitions by combining output presetting techniques together with adequate driving of the output pull-up and pull-down transistors. Tristate operation and zero static power consumption are also provided. The buffer was integrated in a 16-Mb EPROM device. It occupies 0.06 mm/sup 2/ and ensures a better than 15 ns output transition time with a load capacitor of 100 pF. >

1 M-cell 6b/cell analog flash memory for digital storage

This standard flash-EEPROM contains 1 M cells with multi-level programming of up to 64 digital levels per cell, providing a prototype of a 6 Mb memory with 257 Mb/cm/sup 2/ array density.

B/W adaptive image grabber with analog motion vector estimator at 0.3 GOPS

The chip contains a B/W CMOS adaptive video-camera providing quarter common interface format (176/spl times/144 pels), two analog memories, a motion estimator (ME), and a small controller to synchronize computational phases. A modified scheme uses the two analog memories to compare consecutive frames. Good speed and power performance is obtained with only 0.5 dB loss in S/N ratio. A H261-compatible bit stream can be produced to interface with H261 decoders.

An analog memory for a QCIF format image frame storage

An analog memory suitable for storage of a photogenerated image frame is described. An architecture that allows a fast writing rate is presented. The memory has a serial input and eight channels parallel output; it can store a QCIF image (176/spl times/144 pixels) for 1/15 sec with an equivalent precision of 7 bit. Nominal input writing frequency is 2.5 MHz and output reading frequency is 0.833 MHz. The chip needs an external reference clock at 2.5 MHz. The single cell size is 22/spl times/21.2 /spl mu/m. The consumption power of the chip is 6 mW@5 Volts power supply. It has been made using a 0.7 /spl mu/m CMOS technology supplied by SGS-Thomson.

A CMOS micropower input amplifier for hearing aids

This paper describes a CMOS input amplifier for integrated circuits in hearing aids. It has a differential-input differential-output topology, which allows direct driving of cascaded fully-differential processing stages. The adoption of the voltage-to-current conversion and current feedback technique in the amplifying structure, together with the use of a simple differential stage in the offset reduction and in the common-mode feedback loops, allows micropower consumption to be achieved. Experimental results show very good noise and total harmonic distortion performance.