Gilbert Declerck

Theory of the MOS transistor in weak inversion-new method to determine the number of surface states

The drain current I D versus gate voltage V G of an MOST operating in weak inversion, and the influence of surface potential fluctuations on this characteristic have been studied before [1], [2]. The purpose of this paper is to derive an expression of the drain current I D versus the drain voltage V D for devices with a channel length not smaller than 20 µm. It is demonstrated that the surface potential fluctuations do not affect the slope of the I D -V D curve, whereas the density N ss of surface states strongly influences the slope for small drain voltages. This yields a simple and useful technique to determine N ss on MOS transistors.

Explaining the amplitude of RTS noise in submicrometer MOSFETs

A simple-mans model for the random telegraph signal (RTS) noise amplitude in a submicrometer MOSFET is presented. It is shown that the channel resistance modulation for a specific trap can be expressed as a product of the normalized scattering cross section and of the fractional conductivity change. The model qualitatively describes the experimental temperature and drain current dependence of the RTS amplitude and allows evaluation of the influence of the trap location and nature on the wide scatter in values observed. >

The multistable charge-controlled memory effect in SOI MOS transistors at low temperatures

A phenomenon called the MCCM (multistable charge-controlled memory) effect is observed in SOI MOS transistors working at lot temperatures. This MCCM effect essentially results in a controllable setting of the transistor threshold voltage by applying adequate voltage pulses (or up-down voltage sweeps) to one or more electrodes of the structure. A change in threshold voltage of several volts can be obtained. Stability on the order of hours and longer, depending on temperature and operational conditions, is observed. The physics behind the MCCM effect is discussed, and a simple analytical model is proposed. Some new applications based on the MCCM effect are briefly highlighted. >

A self‐aligned cobalt silicide technology using rapid thermal processing

The feasibility of a self‐aligned silicide technology based upon cobalt has been investigated. Silicidation reactions were performed by means of rapid thermal processing. Phase sequence, layer morphology, and reaction kinetics were studied by XRD, SEM, RBS, AES, and TEM. Extremely smooth, highly conductive (16 μΩ cm) CoSi2 films were formed by direct reaction of Co on Si, without significant lateral silicide formation at oxide edges. Shallow arsenic junctions were successfully silicided and low contact resistances were obtained on n+ and p+ Si.

A self-aligned CoSi 2 interconnection and contact technology for VLSI applications

Cobalt silicide is investigated in view of possible application in a self-aligned technology. Extremely smooth, highly conductive CoSi2films are obtained using rapid thermal processing for silicide formation starting from deposited cobalt layers (on Si). The phase formation is studied by XRD and RBS. No lateral silicide formation is observed at contact edges. The influence of Si consumption and dopant behavior on diode performance is studied. Shallow arsenic (0.15 µm deep) and boron (0.3 µm deep) junctions are successfully silicided. Very low contact resistances are obtained between the silicide and n+ and p+ regions. MOS transistors were fabricated with CoSi2on the source, drain, and gate. An increase in current driving capability is noticed while no degradation of other electrical parameters due to the silicide processing steps is observed. At some critical points, comparison is made with the TiSi2process.

Observation of hot-hole injection in NMOS transistors using a modified floating-gate technique

A modified floating-gate technique for measuring small gate currents in MOSFETs with very high resolution (0.01 fA) is described. Using this technique, gate oxide currents due to hot-carrier injection are measured in n-channel MOSFETs. The conventional negative channel hot-electron gate oxide current is observed nearV_{g} = V_{d}and a small positive gate current occurs at low Vg. We argue that the dependencies of this small positive current on Vgand gate length, together with results from a separate floating-source experiment, are consistent only with hot-hole injection.

An analytical model for the MISIS structure in SOI MOS devices

Abstract A general analytical model is presented for the 1-D MISIS (metal-insulator-semiconductor-insulator-semiconductor) structure which occurs in SOI MOS devices. The model takes into account inversion, depletion and accumulation layer widths in both semiconductor regions, fixed isolator charges as well as interface trap charges. The model is compared with numerical simulations and shows very good agreement. Finally, it is applied for calculating the threshold voltage and the subthreshold slope in SOI n MOS transistors and is proven to be superior to conventional analytical models, especially in the thin film regime.

Inadequacy of the classical theory of the MOS transistor operating in weak inversion

The most important characteristics of the MOS transistor operating in weak inversion are discussed. When the drain voltage is greater than a few kT/q it is demonstrated that the drain current can be written as the product of the geometrical factor W/L , the minority carrier diffusion constant, and the inversion charge at the source. In the classical theory, the slope of the In I D versus V G curve is only influenced by the capture of minority carriers by surface states. It is demonstrated that the N ss values obtained from these current measurements are in disagreement with the values found by independent surface states measuring techniques.

The influence of annealing ambient on the shrinkage kinetics of oxidation‐induced stacking faults in silicon

The shrinkage behavior of oxidation‐induced stacking faults (OSF’s) during an annealing in nitrogen, argon, and hydrogen is studied as a function of both annealing temperature and time. Independent of the used gas atmosphere, the OSF shrinkage rate is characterized by an activation energy of 4.9 eV. To explain the different experimental results, an interstitial model for the stacking fault shrinkage is proposed.

The charge transport in a silicon resistor at liquid‐helium temperatures

A simple, one‐dimensional model describing the steady‐state charge transport in a silicon n+nn+ (p+pp+) resistor at liquid‐helium temperatures is derived. This model includes both space‐charge and (contact) barrier limitations to the current flow, typically occurring at these temperatures (T<30 K) in Si. Furthermore, account is made for the interactions between the injected free carriers and the shallow doping atoms, i.e., mainly trapping and shallow level impact ionization, yielding breakdown of the material at rather low electrical fields F. Good qualitative agreement with measured current‐voltage characteristics is found. In addition, the model is able to describe the flow of avalanche‐generated current through the substrate/well of a metal‐oxide‐semiconductor transistor, which is essential for developing a truly analytical description of the low‐temperature drain current kink.