Ludo Deferm

Embedded HIMOS(R) flash memory in 0.35 /spl mu/m and 0.25 /spl mu/m CMOS technologies

In this paper, the performance and reliability characteristics of the 0.35 /spl mu/m/0.25 /spl mu/m High Injection MOS (HIMIOS(R)) technology is described in detail. This flash EEPROM technology relies on source-side injection for programming and Fowler-Nordheim tunneling for erasing, and has been successfully implemented in a 1 Mbit memory array embedded in a 0.35 /spl mu/m CMOS technology, adding only about 30% to the processing cost of digital CMOS. Due to its triple gate structure, the HIMOS(R) cell exhibits a high degree of flexibility and scalability. A fast programming operation (10 /spl mu/s) at 3.3 V supply voltage is combined with an endurance of well over 100000 program/erase cycles, immunity to all possible disturb effects and a retention time that largely exceeds 100 years at 125/spl deg/C. Furthermore, the cell has been scaled to a 0.25 /spl mu/m version, which is a laterally scaled version with the same operating voltages and tunnel oxide thickness. The use of secondary impact ionization is investigated as well and proves to be very promising for future generations when the supply voltage is scaled below 2.5 V.

Read-disturb and endurance of SSI-flash E/sup 2/PROM devices at high operating temperatures

The high-temperature (T) reliability behavior of merged-transistor source side injection (SSI) flash nonvolatile memory (NVM) devices is evaluated in terms of endurance and disturb effects related to stress induced leakage current (SILC) and correlated with the high-T behavior (generation, anneal) of oxide traps. As compared to room-T, program/erase (P/E) cycling at 150/spl deg/C results in an improved endurance due to an enhanced charge emission. The impact of the operating temperature on SILC-related disturb effects, on the other hand, depends on two combined effects in memory cells where large local charge trap-up influences the threshold voltage, V/sub t/: 1) the T-enhanced trap generation and 2) the T-enhanced emission of trapped charge which influences the disturb field. In the case of the HIMOS-cell-which is discussed here-long-term nonvolatility can still be guaranteed at 150/spl deg/C. Finally, bake tests at higher temperatures (250-300/spl deg/C) have been performed in order to evaluate the persistence of the generated damage. It is found that bulk oxide traps are not cured by the bake and, therefore, no long-term relief of SILC-related disturb effects is expected at 150/spl deg/C.

Bonding techniques for single crystal TFT AMLCDs

Transmissive single crystal AMLCD light valves have recently drawn much attention for application in flat panel displays. The active matrix circuits are fabricated on SIMOX wafers and then transferred to glass. Circuit transfer consists in bonding a CMOS processed SIMOX wafer to a Pyrex glass substrate, thinning the SIMOX wafer and opening the contact pads. The pixel electrodes are made in polysilicon to allow standard CMOS processing. This paper discusses the transparency of the poly electrode and evaluates the potential of anodic bonding and adhesive bonding for circuit transfer. A major challenge for anodic bonding is the protection of the device dielectrics against the high voltages applied during bonding. A test chip was designed to investigate different ways of circumventing breakdown of the dielectrics. A method for adhesive bonding is discussed that assures good uniformity of the thickness of the epoxy layer and avoids the inclusion of air bubbles. It is demonstrated that the epoxies are resistant to the chemicals used for thinning the silicon substrate.

High-temperature reliability behavior of SSI-flash E/sup 2/PROM devices

The high-temperature (T) reliability of merged-transistor Source Side Injection (SSI) Flash NVM devices is evaluated in terms of endurance and SILC-related disturbs, and correlated with the high-T behavior (generation, anneal) of oxide traps. As compared to room T, Program/Erase (P/E) cycling at 150/spl deg/C results in an improved endurance due to enhanced charge emission, but also in a reduction of the read-disturb margin. Also, a bake of 72 hrs. at 250/spl deg/C does not cure the generated damage and, therefore, no long-term relief of SILC-related disturb effects is expected at 150/spl deg/C.

Voltage variant source side injection for multilevel charge storage in flash EEPROM

The growing demand for high-density Flash memories in portable computing, smart cards, and telecommunications applications has boosted the efforts on Flash memory cell size scaling and cost reduction. In order to further increase the storage capability and, consequently, reduce the cost per bit of Flash memories, multilevel charge storage (MLCS) techniques have recently gained a lot of interest. Furthermore, MLCS is considered a viable route for increasing embedded Flash density as well. The devices investigated so far, rely either on conventional channel hot electron (CHE) injection or on Fowler-Nordheim tunneling (FNT) for programming. For the first time, this paper shows that source side injection (SSI) is also an excellent candidate for MLCS. The main advantages of SSI for MLCS are the very narrow threshold-voltage distributions after SSI programming, the symmetrical threshold-voltage window and the overerase immunity, which allows an overall wider threshold-voltage window, and hence more separated distributions.