Gin Yee

Clock-delayed domino for adder and combinational logic design

An innovative dynamic logic family, clock-delayed (CD) domino, was developed to provide gates with either inverting or non-inverting outputs, and the high speed and layout compactness of dynamic logic. The characteristics of CD domino are demonstrated in two carry lookahead adder designs and three MCNC combinational logic benchmark circuits. The CD domino designs are compared to designs using static CMOS and standard domino logic. A circuit design tool was developed to automate the design of CD domino circuits. Simulations show a 32-bit CD domino adder comprised of four 8-bit full adders to be 30% faster than a 32-bit standard domino adder, anal a 32-bit CD domino adder comprised of a single 32-bit full adder to be 45% faster. In the combinational logic benchmark circuits, complex inverting and non-inverting gates were used to implement C1355, C3540, and b9. The CD domino circuits were 22%, 43% and 34% faster than their static CMOS counterparts of C1355, C3540 and b9, respectively.

Clock-delayed domino for dynamic circuit design

Clock-delayed (CD) domino is a self-timed dynamic logic family developed to provide single-rail gates with inverting or noninverting outputs. CD domino is a complete logic family and is as easy to design with as static CMOS circuits from a logic design and synthesis perspective. Design tools developed for static CMOS are used as part of a methodology for automating the design of CD domino circuits. The methodology and CD dominos characteristics are demonstrated in the design of a 32-b carry look-ahead adder. The adder was fabricated with MOSISs 0.8-/spl mu/m CMOS process with scalable CMOS design rules that allow a 1.0-/spl mu/m drawn gate length. Measurements of the adder show a worst case addition of 2.1 ns. The CD domino adder is 1.6/spl times/ faster than a dual-rail domino adder designed with the same cell library and technology.

Output prediction logic: a high-performance CMOS design technique

We present Output Prediction Logic (OPL), a technique that can be applied to conventional CMOS logic families to obtain considerable speedups. When applied to static CMOS, OPL retains the restoring character of the logic family, including its high noise margins. Speedups of 2X to 3X over (optimized) conventional static CMOS are demonstrated for a variety of circuits, ranging from chains of gates, to datapath circuits, ranging from chains of gates, to datapath circuits, and to random logic benchmarks. Such speedups are obtained using identical netlists without remapping. When applied to pseudo-nMOS and dynamic families, in combination with remapping to wide-input NORs, OPL yields speedups of 4X to 5X over static CMOS. Since OPL applied to static CMOS is faster than conventional domino logic, and since it has higher noise margins than domino logic, we believe it will scale much better than domino with future processing technologies.

Domino logic synthesis using complex static gates

We address the synthesis of the most general form of a domino gate (dynamic-static domino), which consists of the pairing of a dynamic gate with any inverting static gate. All previous work focused on the synthesis of the most basic domino gate (standard domino), where the inverting static gate is an inverter. We developed a methodology and tools for synthesizing random logic blocks using both dynamic and complex inverting static gates in an alternating fashion. Dynamic-static (DS) domino can be used to reduce both gate levels and clock loading compared to standard domino. Comparisons between DS domino, standard domino, and static CMOS logic families are provided for six MCNC combinational logic benchmark circuits. Spice simulations show DS domino to have an average speed improvement of 53% over static CMOS and an average speed improvement of 17% over standard domino. DS domino also reduced clock loading by an average of 48% over standard domino. The paper introduces DS domino and presents a methodology for synthesizing random logic circuits using DS domino and other monotonic logic families such as Zipper CMOS.

Dynamic logic synthesis

A self-timed dynamic logic family, clock-delayed (CD) domino, was developed to provide non-dual-rail gates with inverting or non-inverting outputs. CD domino circuits are as easy to synthesize as static circuits and synthesis tools developed for static CMOS are used as part of a methodology for automating the design and synthesis of dynamic circuits. The methodology and CD dominos characteristics are demonstrated in the synthesis of five MCNC combinational logic benchmark circuits. Simulations of extracted chip layouts for the circuits show speed improvement factors of 2.17 to 6.28 compared to their static CMOS counterparts.

Monotonic static CMOS and dual V/sub T/ technology

We developed a methodology and tools for synthesizing monotonic static CMOS networks, which consist of alternating low-skewed and high-skewed static gates. When used with a dual V/sub T/ process, monotonic static CMOS can simultaneously reduce standby static power and increase performance by using low V/sub T/ devices in the evaluation networks and making all other devices high V/sub T/. Experimental results show monotonic static CMOS to be 1.67 times faster than traditional static CMOS.

Design and synthesis of monotonic circuits

We developed a methodology and tools for synthesizing monotonic networks, which consist of alternating low-skew and high-skew logic gates. By taking advantage of their reduced input capacitance, lower switching thresholds, and efficient implementation for wide complex gates, monotonic circuits can obtain greater performance compared to static CMOS. Our results show standard domino, dynamic-static domino, monotonic static CMOS, and zipper CMOS to have average speed improvements of 1.57, 1.66, 1.67, and 1.47 times over static CMOS, respectively.

Locally clocked pipelines and dynamic logic

Micropipelines and most of its variants use a delay-insensitive controller to moderate a pipeline. In search of improved performance, we depart from the delay-insensitive model in favor of a bounded-delay model for the controller. In particular, we demonstrate how a general delay-insensitive controller for level-sensitive pipelines can be improved by assuming a bounded-delay model and taking advantage of delay information to make the controller faster and more efficient. The new control scheme is referred to as locally clocked (LC) control. A highly pipelined logic technique called LC dynamic logic is presented that combines the bounded-delay controller for their comments and suggestions. with a latching dynamic logic gate design. Simulations comparing LC control with its delay-insensitive counterpart are presented. Also, an 8 /spl times/ 8 bit multiplier with a maximum frequency of 715 MHz for a 1 /spl mu/m CMOS process that uses LC dynamic logic is presented.

Locally-clocked dynamic logic

Locally-clocked (LC) dynamic logic is a circuit methodology which combines a localized clocking strategy with a robust dynamic gate design to provide a high throughput, low latency circuit solution. LC dynamic logic creates event-driven pipelines which outperform and avoid many of the problems associated with conventional clock-based pipeline techniques. LC dynamic logic was used to implement an 8/spl times/8 bit multiplier design that operates at 715 MHz in a 1.0 /spl mu/m MOSIS process, which exceeds the highest multiplier frequency previously published.

Delay minimization and technology mapping of two-level structures and implementation using clock-delayed domino logic

This paper presents a new delay minimization and technology mapping algorithm for two-level structures (TLS) implemented using clock-delayed (CD) domino logic. We take advantage of CD dominos high-speed, large fan-in NOR and OR gates to increase the speed of a circuit by partial collapsing. The algorithm is delay-driven and the delays are obtained from a characterized CD domino library. The results on eight combinational MCNC benchmark circuits show an average speed improvement of 89% for CD domino with TLS, compared to static CMOS implementations generated by Synopsys. CD domino with TLS using our tools produced on average 44% faster circuits than CD domino benchmarks minimized and mapped using Synopsys. The delay results for CD domino with TLS were on average 22% better than for standard domino.