Tyler Thorp

IC power distribution challenges

With each technology generation, delivering a time-varying current with reduced nominal supply voltage variation is becoming more difficult due to increasing current and power requirements. The power delivery network design becomes much more complex and requires accurate analysis and optimizations at all levels of abstraction in order to meet the specifications. We describe techniques for estimation of the supply voltage variations that can be used in the design of the power delivery network. We also describe the decoupling capacitor hierarchy that provides a low impedance to the increasing high-frequency current demand and limits the supply voltage variations. Techniques for high-level power estimation that can be used for performance vs. power trade-offs to reduce the current and power requirements of the circuit are also presented.

Analysis of blocking dynamic circuits

In order for dynamic circuits to operate correctly, their inputs must be monotonically rising during evaluation. Blocking dynamic circuits satisfy this constraint by delaying evaluation until all inputs have been properly setup relative to the evaluation clock. By viewing dynamic gates as latches, we demonstrate that the optimal delay of a blocking dynamic gate may occur when the setup time is negative. With blocking dynamic circuits, cascading low-skew dynamic gates allows each dynamic gate to tolerate a degraded input level. The larger noise margin provides greater flexibility with the delay versus noise margin tradeoff (i.e., the circuit robustness versus speed tradeoff). This paper generalizes blocking dynamic circuits and provides a systematic approach for assigning clock phases, given delay and noise margin constraints. Using this framework, one can analyze any logic network consisting of blocking dynamic circuits.