Giorgio Cellere

Radiation effects on floating-gate memory cells

We have addressed the problem of threshold voltage (V/sub TH/) variation in flash memory cells after heavy-ion irradiation by using specially designed array structures and test instruments. After irradiation, low V/sub TH/ tails appear in V/sub TH/ distributions, growing with ion linear energy transfer (LET) and fluence. In particular, high LET ions, such as iodine used in this paper, can produce a bit flip. Since the existing models cannot account for large charge losses from the floating gate, we propose a new mechanism, based on the excess of positive charge produced by a single ion, temporarily lowering the tunnel oxide barrier (positive charge assisted leakage current) and enhancing the tunneling current. This mechanism fully explains the experimental data we present.

Anomalous charge loss from floating-gate memory cells due to heavy ions irradiation

We are presenting new data on the charge loss in large floating gate (FG) memory arrays subjected to heavy ion irradiation. Existing models for charge loss from charged FG and generation-recombination after a heavy ion strike are insufficient to justify (or in contrast with) our experimental results. In particular, the charge loss is by far larger than predicted by existing models, it depends on the number of generated holes, not on those surviving recombination, and it is larger for FGs with larger threshold voltage before irradiation. We show that these data can be explained as the effect of two different mechanisms. The first one is a semi-permanent multi trap-assisted tunneling (TAT), which closely resembles anomalous stress induced leakage current (SILC) in electrically stressed devices. The second mechanism is a transient phenomenon responsible for the largest part of the lost FG charge. Detailed physical modeling of this mechanism is still not available, owing to the limited knowledge of the physical background under these phenomena, but three possible models are explored and discussed.

Transient conductive path induced by a Single ion in 10 nm SiO/sub 2/ Layers

Large charge loss can happen in isolated conductive lines when hit by a single high linear energy transfer (LET) ion. We have demonstrated this phenomenon by using floating gate (FG) memory arrays, which allowed us to study it on the basis of a large statistical set of data. Charge loss is by far larger than that expected from a simple generation-recombination model. FGs hit by ions experience a charge loss linearly dependent on ion LET and on the electric field. We are proposing a semi-empirical model based on the idea that a conductive path assimilable to a resistance connects the FG to the substrate during the time (10/sup -14/ s) needed for electrons to escape the tunnel oxide. The model is fully consistent with a broad range of theoretical and experimental results, and has excellent fitting capabilities.

A model for TID effects on floating Gate Memory cells

Four different technologies of floating gate (FG) memory arrays were subjected to /sup 60/Co gamma-rays and 10 keV X-rays irradiation to evaluate their response to the total ionizing dose. The effect of irradiation was a uniform charge loss across the whole array. Irradiation effects can be modeled as the result of two phenomena, namely, the generation of charge in the dielectric layers surrounding the floating gate and its subsequent recombination and drift, and the photoemission of carriers from the charged FG. The second phenomenon is effective at high doses. As a consequence of these two phenomena, devices featuring a smaller FG are less prone to total ionizing dose effects than devices featuring a larger FG, proper of older technological generations. We propose a model that accurately fits experimental data over a broad series of experimental conditions.

Data retention after heavy ion exposure of floating gate memories: analysis and simulation

Floating gate (FG) memories are the most important of current nonvolatile memory technologies. We are investigating the long-term retention issues in advanced Flash memory technologies submitted to heavy ion irradiation. Long tails appear in threshold voltage distribution of cells hit by ions after they have been reprogrammed. This phenomenon is more pronounced in devices with smaller gate area. Results are explained by a new physics-based model of the leakage current flowing through the damaged oxides of FG memory cells. The model calculates the trap-assisted tunneling current through a statistically distributed set of defects by using electron coupling to oxide phonons. The model is used to fit experimental data and to discuss retention properties after heavy ions exposure of future devices, featuring thinner tunnel oxide.

Radiation induced leakage current in floating gate memory cells

Single ions impacting on SiO/sub 2/ layers generate tracks of defects which may result in a Radiation Induced Leakage Current (RILC). This current is usually studied as the cumulative effect of ion-induced defects in capacitors with ultra-thin oxides. We are demonstrating and modeling this phenomenon in 10 nm oxides by using Floating Gate memories. The impact of a single, high-LET ion can result in severe retention problems, due to several electrically active defects, which cooperate to slowly discharge the FG. We are also proposing innovative simulation tools to reproduce this phenomenon. Results from simulations fully explain our results, and also agree with existing data on thinner (4 nm) oxides.

TID Sensitivity of NAND Flash Memory Building Blocks

NAND Flash memories are the leader among high capacity non-volatile memory technologies and are becoming attractive also for radiation harsh environments, such as space. For these applications, a careful assessment of their sensitivity to radiation is needed. In this contribution, we analyze TID effects on the many different building blocks of NAND Flash memories, including the charge pumps, row-decoder, and floating gate array. Since each of these elements have dedicated circuital and technological characteristics, we identify and study the characteristic failure mode for each part.

A review of ionizing radiation effects in floating gate memories

The effects of ionizing radiation on microelectronics are traditionally a concern for devices intended for the space use, but they are becoming important even at ground level. Ionizing radiation effects can be broadly divided in two classes: total ionizing dose (progressive buildup of defects) and single event effects (macroscopic result of a single microscopic event). In both cases, ionizing radiation can lead to severe degradation of device performance, possibly resulting in device failure. This work is a review of literature results concerning both classes of ionizing radiation-related phenomena on floating gate memories. Regardless of its nature, ionizing radiation impacts two aspects of the performance and reliability of floating gate memories: the functionality and the adherence to specifications of the control circuitry, and the degradation of stored information in the array itself.

Angular Dependence of Heavy Ion Effects in Floating Gate Memory Arrays

Single, high energy, high LET, ions impacting on a Floating gate array on grazing or near-grazing angles lead to the creation of long traces of FGs with corrupted information. Up to 30 consecutive devices can be involved in the trace left by a single ion. We demonstrate that charge collection at multiple nodes can be expected as the technology advances. One of the major implications is that the widely adopted cosine law should be used with great care when dealing with modern devices, with sizes smaller than 100 nm.

Error Instability in Floating Gate Flash Memories Exposed to TID

We discuss new experimental results on the post-radiation annealing of Floating Gate errors in Flash memories with both NAND and NOR architecture. We investigate the dependence of annealing on the program level, linking the reduction in the number of Floating Gate errors to the evolution of the threshold voltage of each single cell. To understand the underlying physics we also discuss how temperature affects the number of Floating Gate errors.