Silvia Beltrami

Scaling trends for random telegraph noise in deca-nanometer Flash memories

We present a thorough investigation of the random telegraph noise scaling trend for both NAND and NOR floating-gate flash memories, including experimental and physics-based modeling results. The statistical distribution of the random telegraph noise amplitude is computed using conventional 3D TCAD simulations, establishing a direct connection with cell parameters. The analysis results in a simple formula for the random telegraph noise amplitude standard deviation as a function of cell width, length, substrate doping, tunnel oxide thickness and drain bias. All the simulation results are in good agreement with experimental data and are of utmost importance to understand the random telegraph noise instability and to control it in the development of next generation flash technologies.

TID Sensitivity of NAND Flash Memory Building Blocks

NAND Flash memories are the leader among high capacity non-volatile memory technologies and are becoming attractive also for radiation harsh environments, such as space. For these applications, a careful assessment of their sensitivity to radiation is needed. In this contribution, we analyze TID effects on the many different building blocks of NAND Flash memories, including the charge pumps, row-decoder, and floating gate array. Since each of these elements have dedicated circuital and technological characteristics, we identify and study the characteristic failure mode for each part.

Cycling Effect on the Random Telegraph Noise Instabilities of nor and nand Flash Arrays

The impact of program/erase (P/E) cycling on the random telegraph noise (RTN) threshold voltage instability of NOR and NAND flash memories is studied in detail. RTN is shown to introduce exponential tails in the distribution of the threshold voltage variation between two subsequent read operations on the cells. Tail height is shown to increase as a function of the stress levels, with a larger relative increase for the NAND case. The slope of the distribution instead remains nearly independent of the number of applied P/E cycles. This reveals that trap generation takes place according to the native trap distribution over the active area and means that the tail slope is a basic RTN parameter, depending on the cell process details for a fixed technology. These results are important for the design of the threshold voltage levels in multilevel nor and NAND technologies.

Error Instability in Floating Gate Flash Memories Exposed to TID

We discuss new experimental results on the post-radiation annealing of Floating Gate errors in Flash memories with both NAND and NOR architecture. We investigate the dependence of annealing on the program level, linking the reduction in the number of Floating Gate errors to the evolution of the threshold voltage of each single cell. To understand the underlying physics we also discuss how temperature affects the number of Floating Gate errors.

Key Contributions to the Cross Section of NAND Flash Memories Irradiated With Heavy Ions

Heavy-ion irradiation of NAND flash memories under operating conditions leads to errors with complex, data-dependent signatures. We present upsets due to hits in the floating gate array and in the peripheral circuitry, discussing their peculiarities in terms of pattern dependence and annealing. We also illustrate single event functional interruptions, which lead to errors during erase and program operations. To account for all the phenomena we observe during and after irradiation, we propose an ldquoeffective cross section,rdquo which takes into account the array and peripheral circuitry contributions to the SEU sensitivity, as well as the operating conditions.

Threshold-Voltage Instability Due to Damage Recovery in Nanoscale NAND Flash Memories

This paper presents a detailed investigation of the impact of cycling time and temperature on the threshold-voltage instability arising from damage recovery during data retention on nanoscale nand Flash. Statistical results from the programmed state show that instabilities result, on average, in a threshold-voltage loss, which increases logarithmically with the time elapsed since the end of cycling. The slope of the logarithmic behavior strongly depends on the electric field during data retention, the cycling dose, and the probability level at which the shift of the array cumulative distribution is monitored. Increasing the cycling time and temperature corresponds, instead, to an equivalent delay of the instant at which the first read operation on the array is performed. The delay is studied for a large variety of cycling and retention conditions, extracting the parameters required for a universal damage-recovery metric for nand.

Annealing of Heavy-Ion Induced Floating Gate Errors: LET and Feature Size Dependence

We discuss the room temperature annealing of Floating Gate errors in Flash memories with NAND and NOR architecture after heavy-ion irradiation. We present the evolution of raw bit errors as a function of time after the exposure, examining the annealing dependence on the particle LET, cell feature size, and, for Multi Level Cells, on the program level. The results are explained based on the statistical properties of the cell threshold voltage distributions before and after heavy-ion strikes.

Single Event Effects in NAND Flash Memory Arrays

We are showing for the first time the charge loss due to heavy ion irradiation on Hash memory arrays organized following the NAND architecture. Results complement those previously found for devices featuring a NOR architecture: large charge loss can be expected after the hit of a single ion on a single memory cell. The resulting threshold voltage shift DeltaVTH grows with ion LET and with applied electric field across the tunnel oxide (that is, with the programming conditions) and cannot be explained by simple generation-recombination-transport models. Further, in Floating Gates hit by a single ion a percolation path develops across the tunnel oxide, able to slowly discharge the Floating Gate.

Neutron-Induced Upsets in NAND Floating Gate Memories

We investigate atmospheric neutron effects on floating-gate cells in NAND Flash memory devices. Charge loss is shown to occur, particularly at the highest program levels, causing raw bit errors in multilevel cell NAND, but to an extent that does not challenge current mandatory error correction specifications. We discuss the physical mechanisms and analyze scaling trends, which show a rapid increase in sensitivity for decreasing feature size.

Neutron-induced soft errors in advanced flash memories

Atmospheric neutrons are a known source of Soft Errors (SE), in static and dynamic CMOS memories. This paper shows for the first time that atmospheric neutrons are able to induce SE in Flash memories as well. Detailed experimental results provide an explanation linking the Floating Gate (FG) cell SE rate to the physics of the neutron-matter interaction. The neutron sensitivity is expected to increase with the number of bits per cell and the reduction of the feature size, but the SE issue is within the limit of current ECC capabilities and will remain so in the foreseeable future.