James L. Knighten

Quantifying SMT decoupling capacitor placement in dc power-bus design for multilayer PCBs

Noise on a dc power-bus that results from device switching, as well as other potential mechanisms, is a primary source of many signal integrity (SI) and electromagnetic interference (EMI) problems. Surface mount technology (SMT) decoupling capacitors are commonly used to mitigate this power-bus noise. A critical design issue associated with this common practice in high-speed digital designs is placement of the capacitors with respect to the integrated circuits (ICs). Local decoupling, namely, placing SMT capacitors in proximity to ICs, is investigated in this study. Multilayer PCB designs that employ entire layers or area fills for power and ground in a parallel plate structure are considered. The results demonstrate that local decoupling can provide high-frequency benefits for certain PCB geometries through mutual inductive coupling between closely spaced vias. The associated magnetic flux linkage is between the power and ground layers. Numerical modeling using an integral equation formulation with circuit extraction is used to quantify the local decoupling phenomenon. Local decoupling can effectively reduce high-frequency power-bus noise, though placing capacitors adjacent to ICs may limit routing flexibility, and tradeoffs need to be made based on design requirements. Design curves are generated as a function of power-bus layer thickness and SMT capacitor/IC spacing using the modeling approach to quantify the power-bus noise reduction for decoupling capacitors located adjacent to devices. Measurement data is provided to corroborate the modeling approach.

DC power-bus modeling and design with a mixed-potential integral-equation formulation and circuit extraction

The application of a circuit extraction approach based on a mixed-potential integral equation formulation (CEMPIE) for DC power-bus modeling in high-speed digital designs is detailed. Agreement with measurements demonstrates the effectiveness of the approach. Dielectric losses are included into the calculation of the Greens functions, and thus, incorporated into the rigorous first principles formulation. A SPICE model is then extracted from the discretized integral equation. A quasistatic approximation is used for the Greens functions to keep the extracted circuit elements frequency independent. Previous work has established a necessary meshing criterion in order to ensure accuracy for a given substrate thickness and dielectric constant to a desired frequency. Several power-bus design issues, such as surface mount decoupling and power-plane segmentation, were investigated using the modeling approach. The results and discussions illustrate the application of the method to DC power-bus design for printed circuit and multi-chip module substrates.

Modeling DC power-bus structures with vertical discontinuities using a circuit extraction approach based on a mixed-potential integral equation

The DC power-bus is a critical aspect in high-speed digital circuit designs. A circuit extraction approach based on a mixed-potential integral equation is presented herein to model arbitrary multilayer power-bus structures with vertical discontinuities that include decoupling capacitor interconnects. Greens functions in a stratified medium are used and the problem is formulated using a mixed-potential integral equation approach. The final matrix equation is not solved, rather, an equivalent circuit model is extracted from the first-principles formulation. Agreement between modeling and measurements is good, and the utility of the approach is demonstrated for DC power-bus design.

Frequency-dependent via inductances for accurate power distribution network modeling

In power distribution network (PDN) modeling, interconnection inductance can play a critical role. It often determines the effectiveness of a component, such as a decoupling capacitor. This paper studies a typical one-plane-pair PDN structure with parallel power and ground planes and vertical vias in between. This work improves the conventional lumped circuit model for the PDN by introducing a model for the inductance of each via that is frequency-dependent. This frequency dependency is obtained from a rigorous cavity model formulation. The improved lumped circuit model is validated with the cavity model and the HFSS full-wave model. Further, the frequency-dependent mutual inductance between two vias can have either a positive or a negative value depending on via locations in the PDN structure, which is an interesting property that has not been reported.

Quantifying decoupling capacitor location

The decoupling capacitor location in DC power bus design is a critical design choice for which proven guidelines are not well established. The mutual inductance between two closely spaced vias can have a great impact on the coupling between an IC and a decoupling capacitor. This coupling is a function of the spacing between the IC and capacitor, and spacing between power and ground layers. The impact of the mutual inductance on decoupling, i.e., local versus global decoupling, was studied, using a circuit extraction approach based on a mixed-potential integral equation. Modeling indicates that local decoupling has benefits over global decoupling for certain ranges of IC/capacitor spacing and power layer thickness. Design curves for evaluating local decoupling benefits were generated, which can be used to guide surface mount technology (SMT) decoupling capacitor placement.

Experimental analysis of common mode currents on fibre channel cable shields due to skew imbalance of differential signals operating at 1.0625 Gb/s

The spectral nature of common mode currents induced on high speed differential cables operating at 1.0625 Gb/s was investigated using specially constructed shielded test boards. The source test board provided a source with a selectable amount of delay skew. The load test board provided a simple 150 Ohm differential load. The two boards were placed in separate shielded enclosures with a one meter fibre channel cable connecting them. The common-mode cable shield current and radiated emissions at 3 meters were measured as a function of delay skew. At the fundamental frequency of 531.25 MHz, the common-mode current and radiated emissions increased at a rate of approximately 9 dB/decade of skew. At skew values much lower than the rise time of the signal, the common-mode current increased nearly linearly with skew. The second harmonic was present on the cable shield due to duty cycle distortion and rise and fall time differences inherent in the driver transceiver.

Noise coupling between signal and power/ground nets due to signal vias transitioning through power/ground plane pair

Signal vias are often used to move a signal from one PCB layer to another. As a result, these vias can penetrate power/ground plane pair and cause noise coupling (crosstalk) between signal and power/ground nets. This paper studies the noise coupling mechanism using a segmentation approach combined with a via capacitance model and a plane-pair cavity model. Noise coupling from signal to power/ground, and vice versa, is demonstrated in the modeling results.

SPICE model libraries for via transitions

A procedure of building SPICE models for signal via transitions between printed circuit board layers is presented in this paper. The method of extracting parameters of SPICE models from full-wave simulation tool is demonstrated. Then the validity of SPICE models is studied by comparing the solution from SPICE model with that from the full-wave simulation.

EMI common-mode current dependence on delay skew imbalance in high speed differential transmission lines operating at 1 gigabit/second data rates

EMI-related common-mode currents in a high speed differential transmission line circuits can be generated by delay imbalance (skew) at a rate almost directly proportional to the amount of skew imbalance. Delay skew was shown to generate common-mode currents at a rate of four times that of slew rate skew. Radiated EMI levels were shown to follow increasing common-mode currents. Attention to delay skew imbalance should be an important design consideration at the chip level, the transmission line level and at the load in order to produce high speed differential circuits with low emission characteristics. While models using identified waveforms predict common-mode waveform harmonics that include only odd harmonics, measurements with real devices indicate the presence of all harmonics due to waveform asymmetries, such as dirty cycle distortion and rise/fall time asymmetries.

Noise coupling between power/ground nets due to differential vias transitions in a multilayer PCB

Due to the increase in board density, routing traces on different layers becomes a widely used strategy. Through-hole vias are often used to connect these traces. Those vias that penetrate power/ground plane pairs could cause noise coupling between signal and power/ground nets. At the same time, the need for clean signal transmitted to receivers results in a wide use of differential signals. This paper studies the noise coupling mechanism caused by a differential pair of vias penetrating power/ground plane pair using a physics-based via-plane model combined with transmission line models for traces. A 26-layer printed circuit board with a pair of differential vias have been modeled. The simulated results clearly demonstrate the impact of ground vias and via stubs on noise coupling.