Norman W. Smith

Quantifying SMT decoupling capacitor placement in dc power-bus design for multilayer PCBs

Noise on a dc power-bus that results from device switching, as well as other potential mechanisms, is a primary source of many signal integrity (SI) and electromagnetic interference (EMI) problems. Surface mount technology (SMT) decoupling capacitors are commonly used to mitigate this power-bus noise. A critical design issue associated with this common practice in high-speed digital designs is placement of the capacitors with respect to the integrated circuits (ICs). Local decoupling, namely, placing SMT capacitors in proximity to ICs, is investigated in this study. Multilayer PCB designs that employ entire layers or area fills for power and ground in a parallel plate structure are considered. The results demonstrate that local decoupling can provide high-frequency benefits for certain PCB geometries through mutual inductive coupling between closely spaced vias. The associated magnetic flux linkage is between the power and ground layers. Numerical modeling using an integral equation formulation with circuit extraction is used to quantify the local decoupling phenomenon. Local decoupling can effectively reduce high-frequency power-bus noise, though placing capacitors adjacent to ICs may limit routing flexibility, and tradeoffs need to be made based on design requirements. Design curves are generated as a function of power-bus layer thickness and SMT capacitor/IC spacing using the modeling approach to quantify the power-bus noise reduction for decoupling capacitors located adjacent to devices. Measurement data is provided to corroborate the modeling approach.

Quantifying decoupling capacitor location

The decoupling capacitor location in DC power bus design is a critical design choice for which proven guidelines are not well established. The mutual inductance between two closely spaced vias can have a great impact on the coupling between an IC and a decoupling capacitor. This coupling is a function of the spacing between the IC and capacitor, and spacing between power and ground layers. The impact of the mutual inductance on decoupling, i.e., local versus global decoupling, was studied, using a circuit extraction approach based on a mixed-potential integral equation. Modeling indicates that local decoupling has benefits over global decoupling for certain ranges of IC/capacitor spacing and power layer thickness. Design curves for evaluating local decoupling benefits were generated, which can be used to guide surface mount technology (SMT) decoupling capacitor placement.

SPICE model libraries for via transitions

A procedure of building SPICE models for signal via transitions between printed circuit board layers is presented in this paper. The method of extracting parameters of SPICE models from full-wave simulation tool is demonstrated. Then the validity of SPICE models is studied by comparing the solution from SPICE model with that from the full-wave simulation.

Power integrity investigation of BGA footprints by means of the segmentation method

The engineering of the power delivery network is becoming a fundamental issue in the design of high speed digital systems on PCBs. In fact, providing the required power to the different ICs at the specified noise-free voltage levels allows a correct functioning of the overall PCB systems. More over, the ongoing trend of replacing active devices with peripherally located I/O and PWR/GND pins with areally located I/O and PWR/GND pins (BGA packaged) increases the complexity of the models, when power delivery issues need to be studied in a larger contest, such as the overall PCBs. The employment of the powerful, but simple, concept of the segmentation method allows investigation of the power delivery network of the PCB systems in two fundamental stages. During the first stage, a small cut out of the board corresponding to the BGA footprint is modelled with a 3D full wave simulation tool. During the second stage the equivalent impedance network representation corresponding to this cut out is combined, by means of the segmentation method, with larger pieces of a board, whose network representations can be extracted from the closed form expression of the cavity model approach

Transmission line modeling of vias in differential signals

Signal layer transitions in differential lines are modeled using both FDTD and equivalent circuit methods. The equivalent circuit is developed based on transmission-line reasoning regarding via behavior. Parameters of each transmission-line segment are obtained based on its corresponding physical geometry. The mixed-mode S-parameters from the equivalent circuit and the FDTD modeling are compared. Good agreement is demonstrated in the frequency range from 1 GHz to 20 GHz. The results indicate that vias in differential lines can be modeled as a transmission line for a quick and easy engineering estimation of the differential signal behavior in an environment of signal layer transitions.

The effects of via transitions on differential signals

Vias in differential transmission lines have been modeled using the finite-difference time-domain (FDTD) method. The velocity that the differential signal propagated through the vias was estimated. Differential S-parameters were calculated up to 50 GHz. Below 10 GHz, the differential signal can propagate through vias without much reflection and distortion. However, as frequency increases, the reflection from the vias and the loss of differential power become significant.

Validation of equivalent circuits extracted from S-parameter data for eye-pattern evaluation

S-parameter circuit model extraction is usually characterized by a trade off between accuracy and complexity. Trading one feature for another may or may not affect the goodness of the reconstructed S-parameter data, which are obtained from frequency domain simulations of the models extracted. However, the ultimate test for the validity of these equivalent circuit representations should be left to eye-diagram simulations, which provide useful insights, from an SI point of view, about the degradation of the signal, as it travels through the system. Physics based simplification procedures can be used to tune the models and achieve less complexity, whereas the comparisons of the eye-diagrams may help to quantify the goodness of all these circuits extracted. In fact, the most accurate model is not necessary the best to be used.

The design of a lumped element impedance-matching network with reduced parasitic effects obtained from numerical modeling

This paper presents an impedance-matching network design with numerical modeling of the parasitic effects. A modeling tool CEMPIE (Circuit Extraction approach based on a Mixed Potential Integral Equation formulation) is used to model the board-level parasitics of surface mount technology (SMT) resistors for impedance-matching networks. A 3-layer design of impedance-matching network with 0402 SMT resistors is implemented according to the modeling results. And its performance is demonstrated.