Glenn A. Pomerantz

Inspection/metrology benchmarking on fine pitch design substrate for advanced packages

Integrated silicon packages, such as System in Package, are becoming more popular as electronic packaging solutions, and this technology is driving the need for finer and finer circuit pattern designs. However, optical inspection methodologies are reaching their limits in detecting defects efficiently at these smaller dimensions. This potential technology gap could negatively impact yield performance and quality validation of the substrates or boards used for integrated SiP packages. The lack of inspection capability for fine lines and spaces on panel size substrates and boards used to fabricate SiP carriers supporting high I/O or high bandwidth memory or other components could have a negative impact on yield performance or reliability. This issue has been defined as a technical gap less than “15μm/15μm line space” design rules in the iNEMI package roadmap. iNEMI conducted an industry survey to assess the measurement and inspection capability for fine circuit pattern substrates with features less than 15μms used in high bandwidth applications. The survey is conducted across the entire electronic supply chain from substrate manufacturers to inspection equipment manufacturers, and covers the aspects of product quality and reliability, material and processing, inspection capability, analysis techniques and data management. This paper discusses the findings obtained from the survey results and makes recommendations on metrology capabilities that are required to close the technical gap, with respect to product requirements and process and material capabilities.