Richard F. Indyk

IBM System/390 air-cooled alumina thermal conduction module

Advances in multilayer ceramic (MLC) processing, the use of thin-film metallurgy wiring, and enhancements in thermal dissipation, all described in this paper, represent significant milestones in the evolution of microelectronic packaging technology. The IBM System/390™ air-cooled alumina thermal conduction module (S/390™ alumina TCM) utilizes a 127.5 × 127.5-mm MLC substrate to interconnect as many as 121 VLSI devices and 144 substrate-mounted decoupling capacitors. The substrate provides an array of 648 pads for solder connections to each device, an array of 16 pads for solder connections to each capacitor, and an array of 2772 pins for interconnection with the next package level, and contains approximately 400 m of wiring. The reduced thermal resistance design permits up to 600 W of air-cooling capacity. This paper describes the S/390 alumina TCM fabrication processes and discusses the advances they represent in processing technology, packaging density, and performance. Comparisons to prior technology are made.

End-to-End Integration of a Multi-die Glass Interposer for System Scaling Applications

The processes key to enabling 3D manufacturing, namely, bond, backgrind, and through silicon via (TSV) reveal, are extended for 300 mm glass substrates to fabricate a heterogeneous, multi-die, 2.5D glass interposer. Based on an existing silicon interposer offering, the glass interposer is comprised of multi-level “device” side copper wiring, with line space (L/S) of ≤ 2.5 μm, built using damascene techniques, a 55 μm glass core with through glass vias (TGVs), and multiple UBM levels finished with tin silver (SnAg) C4 bumps. The 300mm TGV wafers are processed on existing silicon wafer manufacturing equipment following established, integrated silicon process flows. Once fully processed, the glass wafers are diced, and the interposer joined to a ceramic carrier by mass reflow. Sub-assemblies are then underfilled, the top die attached, and lidding completed. The final assemblies are tested to evaluate performance of chip to chip interconnects, chip-to-package (through interposer) interconnects, and chip-to-PCB (through interposer and package) interconnects. Results of loss vs frequency measurements are compared, for the glass interposer against the existing silicon interposer results.

A novel methodology for wafer-specific feed-forward management of backside silicon removal by wafer grinding for optimized through silicon via reveal

As 3DIC with through silicon vias (TSV) approaches high volume manufacturing readiness the importance of precision backgrinding has become increasingly more evident. Active management of the backgrinding process has multiple benefits in that it reduces the risk of wafer backside contamination due to premature contact with vias, it enables optimization of the post-thinning residual silicon thickness and the final via reveal process. It can compensate for poor via fabrication depth uniformity and less than ideal temporary bonding total thickness variation (TTV). In this paper we will demonstrate the utility of two tools that when used together can systematically produce thin TSV containing wafers to their optimal thickness while protecting the wafers from particulate contamination. The first instrument in this process scheme is a metrology tool that utilizes IR reflectance to measure the silicon thickness remaining between the bottom of the TSV and backside surface of the wafer. These measurements are then transferred to a special grinding tool that can interpret the data and make changes to the grinding depth within the wafer so as to leave thickness of silicon above the TSVs as uniform as possible. Having removed the bulk of the Si through mechanical grinding and Chem/Mech polishing, the next step in the via-middle process is to remove the last few microns of Si overburden to expose the vias. By leaving a shallower Si layer above the TSV during the thinning process compared to current process, the final via reveal process time can be reduced. Also the need for rework in this process because of the wafer-to-wafer variability in the remaining silicon thickness above the TSV can be eliminated. In addition to measuring the pre-grinding Si thickness, the IR reflectance measurement tool can be used to verify the remaining silicon thickness post grind, establishing thinning process feedback and via reveal process feed-forward data.

Measurement of underfill interfacial and bulk fracture toughness in flip-chip packages

Abstract Flip-chip package reliability is greatly improved by encapsulating the solder interconnections between a polymeric encapsulant or underfill. However, thermo-mechanical stresses within such packages often lead to failures initiating in the vicinity of chip and underfill interface. In this study, we present experimental results geared towards measuring and understanding such failure mechanisms. We provide the bulk fracture toughness of the underfill material and interfacial fracture toughness between the underfill material and the silicon die. The bulk and interfacial fracture toughness measurements are performed as a function of temperature. We use the single edge notch bending test to calculate the bulk fracture toughness of the underfill and to measure the interfacial fracture toughness, we use a novel technique referred to as the wedge delamination method. The wedge delamination method provides substantial advantage in measuring the interfacial fracture toughness for brittle materials over traditional methods. Using the wedge delamination method we compare the fracture strength between the underfill and silicon at the front-face and side-wall interfaces. Additionally, the influence of dicing technique on fracture toughness is also investigated.