Gökçe I. Yayla

Speed and energy analysis of digital interconnections: comparison of on-chip, off-chip, and free-space technologies

We model and compare on-chip (up to wafer scale) and off-chip(multichip module) high-speed electrical interconnections withfree-space optical interconnections in terms of speed performance andenergy requirements for digital transmission in large-scalesystems. For all technologies the interconnections are firstmodeled and optimized for minimum delay as functions of theinterconnection length for both one-to-one and fan-outconnections. Then energy requirements are derived as functions ofthe interconnection length. Free-space optical interconnectionsthat use multiple-quantum-well modulators or vertical-cavitysurface-emitting lasers as transmitters are shown to offer aspeed-energy product advantage as high as 30 over that of the electrical interconnection technologies.

A scalable optoelectronic neural system using free-space optical interconnects

The design of a scalable, fully connected 3-D optoelectronic neural system that uses free-space optical interconnects with silicon-VLSI-based hybrid optoelectronic circuits is proposed. The system design uses a hardware-efficient combination of pulsewidth-modulating optoelectronic neurons and pulse-amplitude-modulating electronic synapses. Low-area, high-linear-dynamic-range analog synapse and neuron circuits are proposed. SPICE circuit simulations and an experimental demonstration of the free-space optical interconnection system are included.

Optically Augmented 3-D Computer

In order to achieve high performance parallel computing in terms of bandwidth versus power consumption and volume, denser and faster means of implementing interconnections while minimizing power and crosstalk are required. Global interconnections can be implemented using free-space interconnect technology and can be coupled to 3-D electronic processing stacks such as those developed at Hughes Research Laboratories or Irvine Sensors Corp. to obtain an optoelectronic 3-D computer with increased throughputs for routing or sorting operations. To this end, the 3-D optoelectronic architecture needs to be designed for optimal performance, light transmitters and receivers need to be integrated with the 3-D VLSI stacks to allow optical inputs and outputs, and free-space optical interconnect elements need to be assembled with the modified 3-D stacks. In this paper, the concepts of the technology and architecture of the optically augmented 3-D computer are evaluated.

A prototype 3D optically interconnected neural network

We report the implementation of a prototype three-dimensional (3D) optoelectronic neural network that combines free-space optical interconnects with silicon-VLSI-based optoelectronic circuits. The prototype system consists of a 16-node input, 4-neuron hidden, and a single-neuron output layer, where the denser input-to-hidden-layer connections are optical. The input layer uses PLZT light modulators to generate optical outputs which are distributed over an optoelectronic neural network chip through space-invariant holographic optical interconnects. Optical interconnections provide negligible fan-out delay and allow compact, purely on-chip electronic H-tree type fan-in structure. The small prototype system achieves a measured 8-bit electronic fan-in precision and a calculated maximum speed of 640 million interconnections per second. The system was tested using synaptic weights learned off system and was shown to distinguish any vertical line from any horizontal one in an image of 4/spl times/4 pixels. New, more efficient light detector and small-area analog synapse circuits and denser optoelectronic neuron layouts are proposed to scale up the system. A high-speed, feed-forward optoelectronic synapse implementation density of up to 10/sup 4//cm/sup 2/ seems feasible using new synapse design. A scaling analysis of the system shows that the optically interconnected neural network implementation can provide higher fan-in speed and lower power consumption characteristics than a purely electronic, crossbar-based neural network implementation. >

Photonic content-addressable memory system that uses a parallel-readout optical disk

We describe a high-performance associative-memory system that can be implemented by means of an optical disk modified for parallel readout and a custom-designed silicon integrated circuit with parallel optical input. The system can achieve associative recall on 128 × 128 bit images and also on variable-size subimages. The systems behavior and performance are evaluated on the basis of experimental results on a motionless-head parallel-readout optical-disk system, logic simulations of the very-large-scale integrated chip, and a software emulation of the overall system.

Energy Requirement and Speed Analysis of Electrical and Free-Space Optical Digital Interconnections

Scaling of VLSI technology has been dramatically increasing microelectronic device densities and speeds. However, the interconnection technology between devices does not advance proportionally. Limited available interconnect materials compatible with VLSI and packaging technologies, increased wire resistance as a result of scaling, residual wire capacitance due to fringing fields and fields between interconnect wires are among the factors that prohibit drastic improvement of the electrical interconnect performance. As a result, the performance of VLSI systems become increasingly more dominated by the performance of long interconnects. To overcome this limitation, free-space optical interconnects have been suggested, where long electrical interconnects are replaced by an optical transmitter, a. photodetector, and interconnection optics between them [2, 10. 13–15,19, 22, 27]. This scheme, although devoid of electrical interconnection para.sitics, has its own difficulties. Unavailability of monolithically integrated optical transmitters on silicon imposes hybrid integration schemes with larger parasitic capacitance and increased cost. Transformation of information from electrical to optical domain and vice versa introduces severe inefficiencies into the energy budget. There are voltage incompatibility issues between some transmitter technologies and VLSI technology as well.

Hardware efficient learning on a 3-D optoelectronic neural system

Discusses the dual-scale topology optoelectronic processor (D-STOP) neural network, a scalable, optically interconnected neural network architecture. The authors present the tandem D-STOP system, which provides the connectivity needed for building fully-parallel neural networks with generic gradient-descent learning rules. The authors review the content addressable network (CAN) learning algorithm, a discrete learning algorithm that provides accelerated learning with reduced hardware requirements. The authors then show how the CAN algorithm can be effectively mapped onto D-STOP, and they investigate associated optoelectronic hardware tradeoffs.<<ETX>>

Prototype 3D optoelectronic neural system

We report the implementation of a prototype 3-D optoelectronic neural system that combines free-space optical interconnects with silicon-VLSI-based hybrid optoelectronic circuits. the prototype system consists of a 16-pixel input, 4-neuron hidden and a single-neuron output layer, where the denser input-to-hidden layer connections are optical. The input layer uses PLZT light modulators to generate optical outputs which are distributed to an optoelectronic analog neural network chip through space invariant holographic optical interconnects. Optical interconnections provide fan-out with negligible delay and allow the use of compact, purely on-chip electronic H-tree fan-in structures. The scalable prototype system achieves 8-bit electronic fan-in precision and a maximum speed of 640 million interconnections per second. The system was tested using synaptic weights learned off-system and applied to a simple line recognition task.© (1993) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

New dimensions in D-STOP neural systems

This paper describes a scalable, highly connected, 3D optoelectronic neural system that uses free-space optical interconnects with silicon-VLSI based hybrid optoelectronic circuits. The system design uses an efficient combination of pulse-width modulating optoelectronic neurons and pulse-amplitude modulating electronic synapses. A prototype system is built and applied to a simple classification problem. An optoelectronic testbench for evaluating learning algorithms suitable for the optoelectronic architecture is implemented. Future directions for the optoelectronic architecture are also discussed; these include limited interconnect neural systems and parallel weight loading that allow receptive fields of arbitrary sizes and connection multiplexing to be achieved.

Optically augmented 3-D computer system

The system design of an optically augmented 3-D computer is presented and evaluated. The system under investigation combines the Hughes 3-D VLSI technology with free-space optoelectronic interconnection modules. The 3-D wafer stacks containing the processing capabilities of the system are assembled with the optoelectronic modules for global communication allowing fast and efficient data routing and/or sorting.