Goomin Jeong

CD control at low K1 optical lithography in DRAM device

In this work, CD control issue at 0.37 K1 optical lithography will be discussed in terms of lens aberration sensitivity. Specific aberration terms that affect CD asymmetry on isolation, word line and storage node layers were investigated by simulation and CD uniformity measurement. The lens aberration was characterized by LITEL ISI (In-Situ Interferometer) and the aberration sensitivity was investigated by Solid-C aerial image simulation. From this result, we can understand the relation between some significant Zernike terms and CD control of DRAM’s critical layers.

Process issues of sub-0.20-μm contact hole patterns for logic devices and DRAM

There are a number of process issues to take into account for patterning sub-0.20micrometers contact holes with optical lithography for Logic device or/and DRAM. Some of the most critical factors for patterning sub-0.20micrometers contact holes are discussed.

Analysis of resist pattern collapse and optimization of DUV process for patterning sub-0.20-μm gate line

We analyzed the local pattern collapse by KLA-2132 in patterning gate line of 0.18 micrometers on the Poly-Si/WSix/Si3N4, where the thickness variation of Si3N4 (Nitride) film affected on the substrate reflectivity. By thickness split experiments of organic bottom anti- reflective layers (ARLs), we showed the effect of thickness variation of Nitride on the resist pattern collapse. We investigated the contribution of various factors to the pattern collapse. First of all, we focused on the CD variation due to substrate reflectivity variation to remove patterns of tolerable aspect ratio. In order to obtain better CD uniformity by tight reflectivity control considering the thickness variation of Nitride film, we optimized anti-reflective layer process using inorganic ARLs. As an inorganic ARL, we used PECVD SiOxNy:H(SiON) of which optical constants were changed by deposition conditions. We compared typical positive-tone DUV resists, of acetal based with environmentally stable chemically amplified photoresist type, to clarify the effect of resist and organic bottom ARL materials.

A study on irregular growing defect mechanism and removal process

Main Topics of a photomask have been CD(Critical Dimension), Overlay and Defects. In side of defects, technique suppressing growing defects which are occurring on a mask surface becomes as important as defect control method during mask manufacturing process. Conventional growing defects arise out of combination of sulfuric ion on a mask surface and environmental facts such as pellicle ingredient, humidity and etc. So Mask cleaning process was driven to reduce sulfuric acid on a mask surface which source of growing defects. And actually various cleaning process has been developed through the elimination of sulfuric acid such as DI, O3 cleaning. Normally Conventional growing defects are removed using DI, SC1 or SPM cleaning according to incidence. But recently irregular growing defects are occurred which are completely distinct from conventional growing defects. Interestingly, irregular growing defects are distributed differently from conventional on a mask. They spread in isolated space patterns and reduce the transmittance so that space pattern size continuously decreased. It causes Wafer Yield loss. Furthermore, irregular growing defects are not fully removed by cleaning which is traditional removal process. In this study, we provide difference between conventional and irregular growing defects based on its characteristic and distributed formation. In addition, we present and discuss removal and control technique about irregular growing defects. For elemental analysis and study, diverse analysis tool was applied such as TEM for checking Cross-Section, AFM for checking the roughness of surface, EDAX, AES, IC for analyzing remained ions and particles on the mask and AIMS.

The verification of printability about marginal defects and the detectability at the inspection tool in sub 50nm node

Since mask design rule is smaller and smaller, Defects become one of the issues dropping the mask yield. Furthermore controlled defect size become smaller while masks are manufactured. According to ITRS roadmap on 2007, controlled defect size is 46nm in 57nm node and 36nm in 45nm node on a mask. However the machine development is delayed in contrast with the speed of the photolithography development. Generally mask manufacturing process is divided into 3 parts. First part is patterning on a mask and second part is inspecting the pattern and repairing the defect on the mask. At that time, inspection tools of transmitted light type are normally used and are the most trustful as progressive type in the developed inspection tools until now. Final part is shipping the mask after the qualifying the issue points and weak points. Issue points on a mask are qualified by using the AIMS (Aerial image measurement system). But this system is including the inherent error possibility, which is AIMS measures the issue points based on the inspection results. It means defects printed on a wafer are over the specific size detected by inspection tools and the inspection tool detects the almost defects. Even though there are no tools to detect the 46nm and 36nm defects suggested by ITRS roadmap, this assumption is applied to manufacturing the 57nm and 45nm device. So we make the programmed defect mask consisted with various defect type such as spot, clear extension, dark extension and CD variation on L/S(line and space), C/H(contact hole) and Active pattern in 55nm and 45nm node. And the programmed defect mask was inspected by using the inspection tool of transmitted light type and was measured by using AIMS 45-193i. Then the marginal defects were compared between the inspection tool and AIMS. Accordingly we could verify whether defect size is proper or not, which was suggested to be controlled on a mask by ITRS roadmap. Also this result could suggest appropriate inspection tools for next generation device among the inspection tools of transmitted light type, reflected light type and aerial image type.

Preliminary verifiability of the aerial image measurement tool over photolithography process

The AIMS (Aerial Image Measurement Tool) measures approximate aerial images to scanner results by adjusting the numerical aperture, illumination type and partial parameters. Accordingly, AIMS tool is used generally to verify the issue points during manufacturing a mask. Normally using a mask for photolithography needs twice verifications. One is the qualification in the mask shop. The other is verification over the photo process using the mask in the wafer fab. If evaluated data at AIMS can be trusted about photo process ability including energy latitude (EL), depth of focus (DOF), CD uniformity (CDU), pattern fidelity and mask defects including repair area, AIMS can function as a first filter before shipping the mask. That means the AIMS data can be used as a preliminary data in the wafer fab. So this study is focused on correlation between measured data at AIMS fab 193i and ArF scanner over the photo process such as EL, DOF, CDU, pattern fidelity and mask defects. First, various patterns are made on attenuated PSM from 80 to 65nm tech. Next correlations are calculated about EL, DOF and CDU by using same optical conditions, measurement points and etc at AIMS and Scanner. Also the aerial images from AIMS are compared with scanner results on defective side how those are matched with each other. Consequently defect printability and CDU map at AIMS were similar to the scanner. In CDU point of view, AIMS exceeds the predictive ability of the mask CD SEM. Moreover it means that wafer CDU can be corrected (improved) independently on the CDU result of the wafer fab by using CDU correctable femto laser tool which reduces transmittance of the mask. Surprisingly, it is possible. And Aerial image about mask defects including repair area is useful to predict the problem of the mask, since it is similar to wafer results. But aerial image compared with wafer image has more difference at 65nm technology node than at 80nm. If adjustment of threshold or measuring method can be done, prediction of the scanner result will have no matter. In conclusion, predictive results at AIMS over photo process can be applied as a preliminary data and it can be used to another index verifying the mask quality.

Mask Inspection method for 45nm node device

Sensitivity of newly developed photo mask inspection tool with reflective optic was evaluated for 45nm DRAM device. To get the required defect sensitivity of mask, printability of mask defect on wafer were simulated using in house simulation tool. Simulation results were compared with inspection results. Characteristic and sensitivity comparison between conventional transmissive and reflective optic tools were evaluated for several types of mask layer of 45nm and 55nm DRAM according to pixel size of detector of inspection tools. This reflective optic with short working distance was equivalent in sensitivity to transmissive optic tool. Mask for 45nm DRAM can be qualified by current status of the art inspection tools.

The study for close correlation of mask and wafer to optimize wafer field CD uniformity

As device pattern size is shrinking to below 65nm on wafer, the small amount of CD variation on wafer field determine the wafer yield. Most of the wafer field CD variations come from mask CD variations across mask field. By correction of dose and transmittance on mask using wafer field CD variation, wafer CD uniformity can be extremely enhanced. To get fine correction of wafer field CD uniformity, we have developed various methods to get close correlation of mask and wafer field CD uniformity by SEM, scatterometry and area CD methods. Especially, area CD from CD-SEM and optical CD measurement tools are developed to represent each area of masks. By optimizing measurement methods, repeatability and correlation of CD uniformity between masks and wafers are enhanced to get more than 0.7 of correlation between mask and wafer. And these give us the correction method to compensate field CD variation of maskCD on wafer. More than mask CD uniformity requirement on 65nm tech of DRAM memory device has been achieved.

OPC accuracy and process window verification methodology for sub-100-nm node

As optical lithography has been pushed down to its theoretical resolution limit, the application of very high NA and aggressive Resolution Enhancement Techniques (RETs) are required in order to ensure necessary resolution and sufficient process window for DRAM cell layouts. The introduction of these technologies, however, leaves very small process window for core and peripheral layouts. In addition, new generation DRAM devices demand very precise CD control of the core and peripheral layouts. It implies that the time has come to keep a very watchful eye on the core and peripheral layouts as well as DRAM cells. Recently, Process Window Qualification (PWQ) technology has been introduced and is known to be very useful to estimate process window of core and peripheral layouts. Also, novel measurement system which can compare SEM image with CAD data is being developed and it can be of great help to evaluate OPC accuracy and feed back the CD deviation to OPC modeling. Last but not least, New Mask Qualification (NMQ) is proposed to verify very low K1 lithography by comparing with relatively high K1 lithography. In this paper, most effective OPC verification methodologies for sub-100nm node are discussed.