Changreol Kim

Evaluation of shadowing and flare effect for EUV tool

One of the major issues introduced by development of Extreme Ultra Violet Lithography (EUV) is high level of flare and shadowing introduced by the system. Effect of the high level flare degrades the aerial images and may introduce unbalanced Critical Dimension Uniformity (CDU) and so on. Also due to formation of the EUV tool, shadowing of the pattern is another concern added from EUVL. Shadowing of the pattern will cause CD variation for pattern directionality and position of the pattern along the slit. Therefore, in order to acquire high resolution wafer result, correction of the shadowing and flare effect is inevitable for EUV lithography. In this study, we will analyze the effect of shadowing and flare effect of EUV alpha demo tool at IMEC. Simulation and wafer testing will be analyzed to characterize the effect of shadowing on angle and slit position of the pattern. Also, flare of EUV tool will be plotted using Kirks disappearing pad method and flare to pattern density will also be analyzed. Additionally, initial investigation into actual sub 30nm Technology DRAM critical layer will be performed. Finally simulation to wafer result will be analyzed for both shadowing and flare effect of EUV tool.

Comparative study of DRAM cell patterning between ArF immersion and EUV lithography

In this paper, we will present comparison of DRAM cell patterning between ArF immersion and EUV lithography which will be the main stream of DRAM lithography. Assuming that the limit of ArF immersion single patterning is around 40nm half pitch, EUV technology is positioned on essential stage because development stage of device manufacturer is going down sub-40nm technology node. Currently lithography technology, in order to improve the limitation of ArF immersion lithography, double patterning technology (DPT) and spacer patterning technology (SPT) have been examined intensively. However, double patterning and spacer patterning technology are not cost-effective process because of complexity of lithography process such as many hard mask stacks and iterative litho, etch process. Therefore, lithography community is looking forward to improving maturity of EUVL technology. In order to overcome several issues on EUV technology, many studies are needed for device application. EUV technology is different characteristics with conventional optical lithography which are non-telecentricity and mask topography effect on printing performance. The printed feature of EUV is shifted and biased on the wafer because of oblique illumination of the mask. Consequently, target CD and pattern position are changed in accordance with pattern direction, pattern type and slit position of target pattern.1 For this study, we make sub-40nm DRAM mask for ArF immersion and EUV lithography. ArF attenuated PSM (Phase Shift Mask) and EUV mask (LTEM) are used for this experiment; those are made and developed by in-house captive maskshop. Simulation and experiment with 1.35NA ArF immersion scanner and 0.25NA EUV full field scanner are performed to characterize EUV lithography and to compare process margin of each DRAM cell. Two types of DRAM cell patterns are studied; one is an isolation pattern with a brick wall shape and another is a storage node pattern with contact hole shape. Line and space pattern is also studied through 24nm to 50nm half pitch for this experiment. Lithography simulation is done by in-house tool based on diffused aerial image model. EM-SUITE and Solid-EUV are also used in order to study characteristics of EUV patterning through rigorous EMF simulation. We also investigated shadowing effect according to pattern shape and design rule respectively. We find that vertical to horizontal bias is around 2nm on 32nm to 40nm half pitch line and space pattern. In the case of DRAM cell, we also find same result with line and space pattern. In view of mask-making consideration, we optimize absorber etch process. So we acquire vertical absorber profile and mask MTT(Mean To Target) within 10% of target CD through several pitch. Process windows and mask error enhancement factors are measured with respect to several DRAM cell pattern. In the case of one dimensional line and space and two dimensional brick wall pattern, vertical pattern shows the best performance through various pitches because of lower shadowing effect than horizontal pattern. But in case of contact hole DRAM cell pattern such as storage node pattern, it has bigger MEF value than one or two dimensional pattern because of independency of shadowing effect. Finally, we compare with 2x, 3x and 4x DRAM cell patterning performance in terms of pattern fidelity, slit CD uniformity and shadowing effect.

A Study of Flare Variation in Extreme Ultraviolet Lithography for Sub-22 nm Line and Space Pattern

One of the critical issues in extreme ultraviolet lithography (EUVL) is flare, which is an integrated light scattering from surface roughness in the EUVL optical system. Flare degrades the control of critical dimension (CD) uniformity across the exposure field. Also, it generates larger CD sensitivity as line and space (L/S) half pitch size decreases. Therefore, we discussed the calculation of accurate flare maps to compensate for flare variation. The influence of three-dimensional (3D) mask topography on flare was investigated with different absorber thicknesses, off-axis illumination angles, and azimuthal angles. Some types of dummy patterns were found to be effective in controlling the flare variation within a L/S patterned target and the average flare of a L/S patterned target. Our studies has definitely made progress in an effective flare variation compensation using a rule-based correction for sub-22 nm L/S half pitch node and beyond.

EUV-patterning characterization using a 3D mask simulation and field EUV scanner

In the field of lithography technology, EUV lithography can be a leading candidate for sub-30 nm technology node. EUVL expose system has different characteristics compared to DUV exposure system. EUV source wavelength is short and no material is transparent to the source. So off-axis reflective optic system is used for patterning in place of on-axis refractive system of DUV system. And different reticle design is needed that consists of 40 pair of Mo/Si multi layer and absorber layer in place of conventional mask. Because of the oblique incidence on the mask, shadowing effect is occurred such as pattern asymmetry, shift and pattern bias depending on pattern orientation. For non-telecentric characteristics of EUV scanner, shadowing effect produces CD variation versus field position[1][2]. Besides, it is well known that EUV scanner has bigger flare than conventional DUV scanner. Therefore, the correction of mask shadowing effect and flare level are one of the important issues for EUV lithography. In this paper, process window and MEF of EUV lithography has been examined by 3D mask simulation. CD variation by shadowing is simulated for various pattern orientations. A shadowing correction method has been calculated due to field position to reduce shadowing effect. And the correction effect is examined by simulation and Experimental results. Principle of radial overlay shift due to field position is verified then the shift length of line and space pattern is calculated.

EUV mask inspection tool using high NA DUV inspection tool

A new inspection system with DUV laser beam and high NA optic for EUV mask has been developed to inspect defects on EUV blank mask and defects by process and handling. The development of new reflective image and optics has increased inspection speed on EUV mask before absorber etch and after absorber etch. Defect classification and operation has increased the productivity of inspection and particle control on EUV mask process. With this new inspection system, defects on blank mask, after resist develop and after etch processed mask were classified and evaluated to install EUV mask process. And defect sensitivities according to various pattern size and process steps were evaluated with required defect size of simulated printing effect on wafer. Designed defect pattern of 46nm node were prepared. Blank masks from Hoya were used. Patterns were exposed using 50KeV electron beam writer. After resist develop, patterns with program defect were inspected. After absorber etching, defects were inspected and evaluated. According to sub film, inspection condition was optimized. Using simulation tool, defects printability were simulated and compared with sensitivity of this inspection tool. Our results demonstrate that this inspection tool is very effective to detect and identify defects and their sources on EUV mask process. In this paper, mask inspection performance of high NA, DUV optic with short working distance was evaluated and described on programmed EUV mask.

Photomask defect detection and inspection: aerial imaging and high resolution inspection strategies

Advanced photomasks exploit complex patterns that show little resemblance to the target printed wafer pattern. The main mask pattern is modified by various OPC and SRAF features while further complexity is introduced as source-mask-optimization (SMO) technologies experience early adoption at leading manufacturers. The small size and irregularity of these features challenge the mask inspection process as well as the mask manufacturing process. The two major concerns for mask inspection and qualification efficacy of advanced masks are defect detection and photomask inspectability. Enhanced defect detection is critical for the overall mask manufacturing process qualification which entails characterization of the systematic deviations of the pattern. High resolution optical conditions are the optimal solution for manufacturing process qualification as well as a source of additional information for the mask qualification. Mask inspection using high resolution conditions operates on an optical image that differs from the aerial image. The high resolution image closely represents the mask plane pattern. Aerial imaging mode inspection conditions, where the optics of the inspection tool emulates the lithography manufacturing conditions in a scanner, are the most compatible imaging solution for photomask pattern development and hence mask inspectability. This is an optimal environment for performing mask printability characterization and qualification. In this paper we will compare the roles of aerial imaging and high resolution mask inspection in the mask house.

The source of carbon contamination for EUV mask production

As the semiconductor industry requires lithography suitable for 32-nm node, extreme ultraviolet lithography (EUVL) has the potential to provide this capability for the mass fabrication of semiconductor devices. But because an extreme ultraviolet (EUV) lithography exposure system is operated in vacuum, during irradiation by EUV light, hydrocarbons are decomposed in vacuum1-3, for example, by the out-gassing from EUV mask, and contaminate the surface of imaging optics which is coated with Mo/Si multi-layers with carbon. Thus, this contamination not only reduces the reflectivity of the Mo/Si multi-layers of imaging optics and degrades the exposure uniformity, but also degrades the resolution of the imaging optics. In this study, as we examined the volume of the out-gassing and the species from EUV mask after every process for EUV mask production, we will control the carbon contamination of EUV mask. Keywords: EUV, carbon contamination, reflectance, out-gassing

Optimized Multigrid Strategy for Accurate Flare Modeling with Three-Dimensional Mask Effect in Extreme-Ultraviolet Lithography

Extreme-ultraviolet (EUV) lithography has many critical challenges regarding its implementation in the semiconductor industry. One of the main challenges is flare, the unwanted total integrated light scattering at the wafer level, which reduces the critical dimension and imaging performance. Therefore, EUV flare has been intensively studied and has been compensated by a rule-based method for many years. However, there are few results with regard to developing more accurate and feasible flare-modeling techniques to enable us to satisfy the criteria of the sub-22 nm half pitch (HP) technology node and beyond. In this work, we studied an improved flare-modeling technique considering the interaction of scattered EUV light with a three-dimensional EUV mask topography in order to obtain an accurate flare distribution and an optimized multigrid strategy for generating a flare map over the full-field scale. Also, we proposed a flare-modeling technique based on the pedestal model, which we developed using novel effective reflection coefficients in order to achieve sufficient accuracy. Such an approach is thought to be needed instead of the conventional pattern density approach in preparation for upcoming advanced HP technology nodes or for different absorber materials and illumination angles. Lastly, the need for a flare map shift to compensate for the mask defocus error is introduced and some flare evaluations of mask patterns used in the exposure-dose-monitoring technique were performed.

A study on irregular growing defect mechanism and removal process

Main Topics of a photomask have been CD(Critical Dimension), Overlay and Defects. In side of defects, technique suppressing growing defects which are occurring on a mask surface becomes as important as defect control method during mask manufacturing process. Conventional growing defects arise out of combination of sulfuric ion on a mask surface and environmental facts such as pellicle ingredient, humidity and etc. So Mask cleaning process was driven to reduce sulfuric acid on a mask surface which source of growing defects. And actually various cleaning process has been developed through the elimination of sulfuric acid such as DI, O3 cleaning. Normally Conventional growing defects are removed using DI, SC1 or SPM cleaning according to incidence. But recently irregular growing defects are occurred which are completely distinct from conventional growing defects. Interestingly, irregular growing defects are distributed differently from conventional on a mask. They spread in isolated space patterns and reduce the transmittance so that space pattern size continuously decreased. It causes Wafer Yield loss. Furthermore, irregular growing defects are not fully removed by cleaning which is traditional removal process. In this study, we provide difference between conventional and irregular growing defects based on its characteristic and distributed formation. In addition, we present and discuss removal and control technique about irregular growing defects. For elemental analysis and study, diverse analysis tool was applied such as TEM for checking Cross-Section, AFM for checking the roughness of surface, EDAX, AES, IC for analyzing remained ions and particles on the mask and AIMS.

The verification of printability about marginal defects and the detectability at the inspection tool in sub 50nm node

Since mask design rule is smaller and smaller, Defects become one of the issues dropping the mask yield. Furthermore controlled defect size become smaller while masks are manufactured. According to ITRS roadmap on 2007, controlled defect size is 46nm in 57nm node and 36nm in 45nm node on a mask. However the machine development is delayed in contrast with the speed of the photolithography development. Generally mask manufacturing process is divided into 3 parts. First part is patterning on a mask and second part is inspecting the pattern and repairing the defect on the mask. At that time, inspection tools of transmitted light type are normally used and are the most trustful as progressive type in the developed inspection tools until now. Final part is shipping the mask after the qualifying the issue points and weak points. Issue points on a mask are qualified by using the AIMS (Aerial image measurement system). But this system is including the inherent error possibility, which is AIMS measures the issue points based on the inspection results. It means defects printed on a wafer are over the specific size detected by inspection tools and the inspection tool detects the almost defects. Even though there are no tools to detect the 46nm and 36nm defects suggested by ITRS roadmap, this assumption is applied to manufacturing the 57nm and 45nm device. So we make the programmed defect mask consisted with various defect type such as spot, clear extension, dark extension and CD variation on L/S(line and space), C/H(contact hole) and Active pattern in 55nm and 45nm node. And the programmed defect mask was inspected by using the inspection tool of transmitted light type and was measured by using AIMS 45-193i. Then the marginal defects were compared between the inspection tool and AIMS. Accordingly we could verify whether defect size is proper or not, which was suggested to be controlled on a mask by ITRS roadmap. Also this result could suggest appropriate inspection tools for next generation device among the inspection tools of transmitted light type, reflected light type and aerial image type.