Goon-Ho Park

High-Performance Graphene Field-Effect Transistors With Extremely Small Access Length Using Self-Aligned Source and Drain Technique

Self-aligned source/drain (S/D) graphene field-effect transistors (GFETs) with extremely small access lengths were successfully fabricated using a simple device fabrication process without sidewall spacer formation. The self-aligned S/D GFET exhibits superior electrical characteristics, such as the intrinsic carrier mobility of 6100 cm2/Vs, the gate leakage current of 10-10-10-9 A and the contact resistance of 412 Ωμm. In particular, a cutoff frequency of 13 GHz was achieved with a rather large gate length (LG= 3 μm), which demonstrates the promising future of this self-aligned GFET.

Solution-processed Al2O3 gate dielectrics for graphene field-effect transistors

The performance of actual graphene FETs suffers significant degradation from that expected for pristine graphene, which can be partly attributed to the onset of defects and the doping of the graphene induced during the fabrication of gate dielectric layers. These effects are mainly due to high-temperature processes such as postdeposition annealing. Here, we propose a novel low-temperature method for the fabrication of gate dielectrics, which consists of the natural oxidation of an ultrathin Al layer and a sol–gel process with oxygen plasma treatment to form an Al2O3 layer. The method results in a significant reduction of defects and doping in graphene, and devices fabricated by this method show an intrinsic carrier mobility as high as 9100 cm2 V−1 s−1.

High-performance self-aligned graphene transistors fabricated using contamination- and defect-free process

A contamination- and defect-free process is proposed for self-aligned graphene field-effect transistor (GFET) fabrication using a protective gold layer and by its etching. The gold layer serves as an electrode metal for both the source and drain. GFETs fabricated by this method exhibit superior electrical characteristics, such as an intrinsic carrier mobility of 8900 cm2 V−1 s−1 and a series resistance of 1520 Ω µm, which is ascribed to the effective blocking of unwanted contamination and defect formation as well as to the reduction in access length due to the self-aligned configuration. Our approach is quite promising as a device fabrication method for high-performance GFETs.

Charge Trapping Characteristics of Variable Oxide Thickness Tunnel Barrier with SiO2/HfO2 or Al2O3/HfO2 Stacks for Nonvolatile Memories

Charge trapping characteristics of asymmetrical tunnel barriers consisting of different dielectric materials were investigated for application of nonvolatile memory devices. A thin HfO2 layer stacked on ultrathin SiO2 layer (SiO2/HfO2 tunnel barrier) revealed higher current sensitivity to applied gate voltage than the conventional single SiO2 tunnel barrier. On the other hand, the electron trapping of the tunnel barriers increased with the thickness of HfO2 layer. Thus, a thin HfO2 layer is promising for the engineered tunnel barriers, while a thick HfO2 layer is appropriate for charge trapping layers for high-integrated nonvolatile memories. Meanwhile, an ultrathin Al2O3/HfO2 tunnel barrier also revealed good electrical characteristics and is suitable for low temperature fabrication process.

Improved Electrical Characteristics of Symmetrical Tunneling Dielectrics Stacked with SiO 2 and Si 3 N 4 Layers by Annealing Processes for Non-volatile Memory Applications

The electrical characteristics and annealing effects of tunneling dielectrics stacked with and were investigated. I-V characteristics of band gap engineered tunneling gate stacks consisted of (NON), (ONO) dielectrics were evaluated and compared with single layer using the MOS (metal-oxide-semiconductor) capacitor structure. The leakage currents of engineered tunneling barriers (ONO, NON stacks) are lower than that of the conventional single layer at low electrical field. Meanwhile, the engineered tunneling barriers have larger tunneling current at high electrical field. Furthermore, the increased tunneling current through engineered tunneling barriers related to high speed operation can be achieved by annealing processes.

Evaluation of SGOI wafer with different concentrations of Ge using pseudo-MOSFET

The electrical characteristic of SiGe-on-SOI (SGOI) wafer with different Ge concentration were evaluated by pseudo-MOSFET. Epitaxial SiGe layers was grown directly on top of SOI with Ge concentrations of 16.2, 29.7, 34.3 and 56.5 at.%. As Ge concentration increased, leakage current increased and threshold voltage shifted from 3 V to 7 V in nMOSFET, from -7 V to -6 V in pMOSFET. The interface states between buried oxide and top of Si was significantly increased by the rapid thermal annealing (RTA) process, and so the electrical characteristic of SGOI wafer degraded. On the other hand, additional post RTA annealing (PRA) showed that it was effective in decreasing the interface states generated by RTA processes and the electrical characteristic of SGOI wafer enhanced higher than initial state.