Gopal Raghavan

A 3.2-GHz second-order delta-sigma modulator implemented in InP HBT technology

This paper presents a second-order delta-sigma (/spl Delta//spl Sigma/) modulator fabricated in a 70 GHz (f/sub T/), 90 GHz (f/sub max/) AlInAs-GaInAs heterojunction bipolar transistor (HBT) process on InP substrates. The modulator is a continuous time, fully differential circuit operated from /spl plusmn/5 volt supplies and dissipates 1 W. At a sample rate of 3.2 GHz and a signal bandwidth of 50 MHz (OSR=32100 MSPS Nyquist rate) the modulator demonstrates a Spur Free Dynamic Range (SFDR) of 71 dB (12-b dynamic range). The modulator achieves the ideal signal-to-noise ratio (SNR) of 55 dB for a second-order modulator at an oversampling ratio (OSR) of 32. The design of a digital decimation filter for this modulator is complete and the filter is currently in fabrication in the same technology. This work demonstrates the first /spl Delta//spl Sigma/ modulator in III-V technology with ideal performance and provides the foundation for extending the use of /spl Delta//spl Sigma/ modulator analog-to-digital converters (ADCs) to radio frequencies (RF). >

Architecture, design, and test of continuous-time tunable intermediate-frequency bandpass delta-sigma modulators

This paper examines the architecture, design, and test of continuous-time tunable intermediate-frequency (IF) fourth-order bandpass delta-sigma (BP /spl Delta//spl Sigma/) modulators. Bandpass modulators sampling at high IFs (/spl sim/100 MHz) allow direct sampling of the RF signal-reducing analog hardware and make it easier to realize completely software programmable receivers. This paper presents circuit design of and test results from continuous-time fourth-order BP /spl Delta//spl Sigma/ modulators fabricated in AlInAs/GaInAs heterojunction bipolar technology with a peak unity current gain cutoff frequency (f/sub T/) of 80 GHz and a maximum frequency of oscillation (f/sub MAX/) of about 130 GHz. Operating from /spl plusmn/5-V power supplies, a fabricated 180-MHz IF fourth-order /spl Delta//spl Sigma/ modulator sampling at 4 GS/s demonstrates stable behavior and achieves 75.8 dB of signal-to-(noise+distortion)-ratio (SNDR) over a 1-MHz bandwidth. Narrowband performance (/spl sim/1 MHz) performance of these modulators is limited by thermal/device noise while broadband performance (/spl sim/60 MHz), is limited by quantization noise. The high sampling frequency (4 GS/s) in this converter is dictated by broadband (60 MHz) performance requirements.

A bandpass /spl Sigma//spl Delta/ modulator with 92 dB SNR and center frequency continuously programmable from 0 to 70 MHz

Use of a bandpass /spl Sigma//spl Delta/ modulator permits direct conversion of an analog signal to digital form at IF frequencies. This allows the ADC to be moved closer to the receiver front end. Moving the digital interface closer to the antenna reduces receiver analog circuit complexity, eliminates DC-offset cancellation, inphase/quadrature (I/Q) gain calibration, dual I/Q mixers and improves system robustness as mixing is in the digital domain. This second-order bandpass /spl Sigma//spl Delta/ modulator is targeted for an airborne radar system but is also expected to find use in a variety of communications applications. Measurements yield signal to noise+distortion ratio (SNR) from 92 dB (15 b) in narrowband ( 366 kHz) to 44 dB (7 b) in broadband (62.6 MHz) about a center frequency of 55.5 MHz. Modulator sampling rate is 4 GHz and it is implemented in AlInAs-InGaAs HBT technology. The performance represents an improvement of approximately a factor of 10 in bandwidth, resolution and center frequency over other reported bandpass modulators.

Highly integrated InP HBT optical receivers

This paper presents two highly integrated receiver circuits fabricated in InP heterojunction bipolar transistor (HBT) technology operating at up to 2.5 and 7.5 Gb/s, respectively. The first IC is a generic digital receiver circuit with CMOS-compatible outputs. It integrates monolithically an automatic-gain-control amplifier, a digital clock and data recovery circuit, and a 1:8 demultiplexer, and consumes an extremely low 340 mW of power at 3.3 V, including output buffers. It can realize a full optical receiver when connected to a photo detector/preamplifier front end. The second circuit is a complete multirate optical receiver application-specific integrated circuit (ASIC) that integrates a photodiode, a transimpedance amplifier, a limiting amplifier, a digital clock and data recovery circuit, a 1:10 demultiplexer, and the asynchronous-transfer-mode-compatible word synchronization logic. It is the most functionally complex InP HBT optoelectronic integrated circuit reported to date. A custom package has also been developed for this ASIC.