Robert H. Walden

Analog-to-digital converter survey and analysis

Analog-to-digital converters (ADCs) are ubiquitous, critical components of software radio and other signal processing systems. This paper surveys the state-of-the-art of ADCs, including experimental converters and commercially available parts. The distribution of resolution versus sampling rate provides insight into ADC performance limitations. At sampling rates below 2 million samples per second (Gs/s), resolution appears to be limited by thermal noise. At sampling rates ranging from /spl sim/2 Ms/s to /spl sim/4 giga samples per second (Gs/s), resolution falls off by /spl sim/1 bit for every doubling of the sampling rate. This behavior may be attributed to uncertainty in the sampling instant due to aperture jitter. For ADCs operating at multi-Gs/s rates, the speed of the device technology is also a limiting factor due to comparator ambiguity. Many ADC architectures and integrated circuit technologies have been proposed and implemented to push back these limits. The trend toward single-chip ADCs brings lower power dissipation. However, technological progress as measured by the product of the ADC resolution (bits) times the sampling rate is slow. Average improvement is only /spl sim/1.5 bits for any given sampling frequency over the last six-eight years.

A 3.2-GHz second-order delta-sigma modulator implemented in InP HBT technology

This paper presents a second-order delta-sigma (/spl Delta//spl Sigma/) modulator fabricated in a 70 GHz (f/sub T/), 90 GHz (f/sub max/) AlInAs-GaInAs heterojunction bipolar transistor (HBT) process on InP substrates. The modulator is a continuous time, fully differential circuit operated from /spl plusmn/5 volt supplies and dissipates 1 W. At a sample rate of 3.2 GHz and a signal bandwidth of 50 MHz (OSR=32100 MSPS Nyquist rate) the modulator demonstrates a Spur Free Dynamic Range (SFDR) of 71 dB (12-b dynamic range). The modulator achieves the ideal signal-to-noise ratio (SNR) of 55 dB for a second-order modulator at an oversampling ratio (OSR) of 32. The design of a digital decimation filter for this modulator is complete and the filter is currently in fabrication in the same technology. This work demonstrates the first /spl Delta//spl Sigma/ modulator in III-V technology with ideal performance and provides the foundation for extending the use of /spl Delta//spl Sigma/ modulator analog-to-digital converters (ADCs) to radio frequencies (RF). >

A deep-submicrometer microwave/digital CMOS/SOS technology

0.35- mu m complementary metal-oxide-semiconductor (CMOS)/silicon-on-sapphire (SOS) n- and p-channel MOSFETs with a metal-over-polysilicon T-gate structure for monolithic microwave integrated circuit (MMIC) and digital applications are reported. The measured values for the current-gain cutoff frequency f/sub T/ were >or=20 GHz for both n-channel and p-channel devices, and the values for the unilateral power-gain cutoff frequency f/sub max/ were 37 GHz for the p-channel and 53 GHz for the n-channel MOSFETs. The low effective resistance of the T-gate structure contributed to the very high f/sub max/ values. It is believed that these are the highest f/sub T/ and f/sub max/ values ever reported for MOS devices. The potential of SOS submicrometer MOSFETs for microwave circuit applications is demonstrated.<<ETX>>

InP-HBT chip-set for 40-Gb/s fiber optical communication systems operational at 3 V

A chip set for a 40 Gb/s fiber optical communication system has been designed and fabricated. On-wafer measurements have been performed to verify circuit operations. As far as available measurement capabilities show, all circuits are functionally fulfilling specifications for 10 Gb/s operation at less than or equal to 3 V supply voltage. During the design phase especially the influence of interconnects on signal integrity was investigated and the results were implemented for automatic extraction. All the circuits were operational after the first processing round. No redesign was necessary.

An InP-based HBT fab for high-speed digital, analog, mixed-signal, and optoelectronic ICs

Integrated circuits (ICs) utilizing indium phosphide based heterojunction bipolar transistors (HBTs) have set numerous speed and bandwidth records over the past several years. This paper describes the extension of that HBT IC technology to an IC fabrication capability which is quite versatile in being able to produce digital, analog, mixed signal, and optoelectronic ICs within the same process. This enables the fab line to quickly respond to varying demands. Three ICs are discussed which exemplify the capability of this fab: (1) a 7 GHz 12-bit accumulator; (2) a nearly ideal continuous-time-sampling second-order /spl Delta//spl Sigma/ modulator operating at a 3.2 GHz sample rate; and (3) a monolithic 4-channel optoelectronic receiver array capable of 20 Gb/s operation.

A bandpass /spl Sigma//spl Delta/ modulator with 92 dB SNR and center frequency continuously programmable from 0 to 70 MHz

Use of a bandpass /spl Sigma//spl Delta/ modulator permits direct conversion of an analog signal to digital form at IF frequencies. This allows the ADC to be moved closer to the receiver front end. Moving the digital interface closer to the antenna reduces receiver analog circuit complexity, eliminates DC-offset cancellation, inphase/quadrature (I/Q) gain calibration, dual I/Q mixers and improves system robustness as mixing is in the digital domain. This second-order bandpass /spl Sigma//spl Delta/ modulator is targeted for an airborne radar system but is also expected to find use in a variety of communications applications. Measurements yield signal to noise+distortion ratio (SNR) from 92 dB (15 b) in narrowband ( 366 kHz) to 44 dB (7 b) in broadband (62.6 MHz) about a center frequency of 55.5 MHz. Modulator sampling rate is 4 GHz and it is implemented in AlInAs-InGaAs HBT technology. The performance represents an improvement of approximately a factor of 10 in bandwidth, resolution and center frequency over other reported bandpass modulators.

Highly integrated InP HBT optical receivers

This paper presents two highly integrated receiver circuits fabricated in InP heterojunction bipolar transistor (HBT) technology operating at up to 2.5 and 7.5 Gb/s, respectively. The first IC is a generic digital receiver circuit with CMOS-compatible outputs. It integrates monolithically an automatic-gain-control amplifier, a digital clock and data recovery circuit, and a 1:8 demultiplexer, and consumes an extremely low 340 mW of power at 3.3 V, including output buffers. It can realize a full optical receiver when connected to a photo detector/preamplifier front end. The second circuit is a complete multirate optical receiver application-specific integrated circuit (ASIC) that integrates a photodiode, a transimpedance amplifier, a limiting amplifier, a digital clock and data recovery circuit, a 1:10 demultiplexer, and the asynchronous-transfer-mode-compatible word synchronization logic. It is the most functionally complex InP HBT optoelectronic integrated circuit reported to date. A custom package has also been developed for this ASIC.

A deep-submicrometer analog-to-digital converter using focused-ion-beam implants

The use of focused-ion-beam (FIB) technology to realize multiple MOSFET threshold voltages in the comparators of an experimental 4-b flash analog-digital converter (ADC) is discussed. The result is a simpler design in that each comparator is a CMOS inverter and the resistor ladder is eliminated. The ADC was fabricated in CMOS/SOS with comparator channel lengths of 0.5 mu m and digital device channel lengths of 0.25 mu m. Measurements of signal-to-noise ratio and analog bandwidth indicate that the ADC can function as a Nyquist converter at sampling frequencies up to 400 MHz. Better than 3-b resolution was observed for a wide range of conditions, including sampling rates above 1 GHz. The power dissipation apart from the output buffers (driving 50- Omega loads) was less than 100 mW, even at sampling rates >or=1 GHz. This 370 MOSFET circuit is one of the most complex ICs yet built with 0.25- mu m CMOS. A promising application is in oversampled ADC architectures, where this circuit would function effectively as an internal high-speed quantizer. >

Integrated optoelectronic circuits with InP-based HBTs

Integrated optoelectronic circuits that are capable of very high speeds or high functionality have been demonstrated using InP-based heterojunction bipolar transistors (HBTs). Optoelectronic receivers contain photodetectors fabricated from the same epitaxial material structure as the HBTs. High-functionality digital receivers, analog receiver arrays as well as analog-to-digital converters have been realized. Optoelectronic modulation circuits for signal transmission also contain separately grown, surface-coupled multiple- quantum-well (MQW) modulators.

40 Gb/s, 3 volt InP HBT ICs for a fiber optic demonstrator system

We have designed and fabricated an InP HBT chip set intended for a 40 Gb/s fiber optic demonstrator system. The chip set consists of 14 different digital- and analog-ICs, and the project is a joint-venture between Ericsson Microwave Systems AB and Hughes Research Laboratories. The project goal is to demonstrate 40 Gb/s fiber optical operation, to learn how to design very high speed/high frequency integrated circuits, and to expand our knowledge on circuit behaviour prediction.