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Dive into the research topics where Gordon A. Haller is active.

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Featured researches published by Gordon A. Haller.


workshop on microelectronics and electron devices | 2007

Metal Gate Recessed Access Device (RAD) for DRAM Scaling

Nirmal Ramaswamy; Venkat Ananthan; David K. Hwang; Ravi Iyer; Chandra Mouli; Allen McTeer; Sanh D. Tang; Kunal R. Parekh; Tim Owens; Young Pil Kim; Nanda Palaniappan; Jian Li; Steve Groothuis; Gordon A. Haller; Shixin Wang

A functional DRAM with higher data retention characteristics than a planar access device has been demonstrated, using a metal gate recessed access device (RAD). Chemical vapor deposition (CVD) and atomic layer deposition (ALD) were used to deposit titanium nitride (TiN) and tantalum nitride (TaN), respectively. CVD TiN and ALD TaN-CVD TiN laminate gate stacks were integrated with a RAD module. ALD TaN-CVD TiN laminate gates showed enhanced drive current (IDS), higher transconductance (GM), higher mobility (¿EFF) and reduced off current (IOFF) characteristics compared to CVD TiN gates. Device characteristics and reliability data for both the planar devices and RADs are presented. The ALD TaN-CVD TiN laminate metal gate RAD showed much improved data retention characteristics compared to a conventional planar device with a poly silicon gate. The optimum thickness of ALD TaN in the laminate stack is discussed.


Archive | 2008

Semiconductor Memory Device

Gordon A. Haller; Sanh D. Tang; Steve Cummings


Archive | 1990

Process for fabricating a DRAM array having feature widths that transcend the resolution limit of available photolithography

Tyler A. Lowrey; Randal W. Chance; D. Mark Durcan; Ruojia Lee; Charles H. Dennison; Yauh-Ching Liu; Pierre C. Fazan; Fernando Gonzalez; Gordon A. Haller


Archive | 2013

Methods of fabricating a memory device

Gordon A. Haller; Sanh D. Tang; Steve Cummings


Archive | 2008

Peripheral gate stacks and recessed array gates

Thomas A. Figura; Gordon A. Haller


Archive | 2006

Memory cell layout and process flow

Gordon A. Haller; David K. Hwang; Sanh D. Tang; Ceredig Roberts


Archive | 2007

Memory structure for reduced floating body effect

Gordon A. Haller


Archive | 2006

One-transistor memory cell with bias gate

Sanh D. Tang; Gordon A. Haller; Daniel H. Doyle


Archive | 1990

Process for fabricating, on the edge of a silicon mesa, a MOSFET which has a spacer-shaped gate and a right-angled channel path

Tyler A. Lowrey; Randal W. Chance; D. Mark Durcan; Pierre C. Fazan; Fernando Gonzalez; Gordon A. Haller


Archive | 2005

Methods of forming devices associated with semiconductor constructions

Hasan Nejad; Gordon A. Haller; Thomas A. Figura; Ravi Iyer

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