Greg Dermer

Neutron soft error rate measurements in a 90-nm CMOS process and scaling trends in SRAM from 0.25-/spl mu/m to 90-nm generation

The neutron soft error rate (SER) dependency on voltage and area was measured for a state-of-the-art 90-nm CMOS technology. The SER increased by 18% for a 10% reduction in voltage, and scaled linearly with diode area. The measured SER per bit of SRAMs in 0.25 /spl mu/m, 0.18 /spl mu/m, 0.13 /spl mu/m, and 90 nm showed an increase of 8% per generation.

Ultra-low voltage circuits and processor in 180nm to 90nm technologies with a swapped-body biasing technique

A low-voltage swapped-body biasing technique where PMOS bodies are connected to ground and NMOS bodies to Vcc is evaluated. Available measurements show more than 2.6x frequency improvement at 0.5V Vcc and the ability to reduce Vcc by 0.2V for the same frequency compared to no body bias in 180 to 90nm CMOS technologies.

A TCP offload accelerator for 10 Gb/s Ethernet in 90-nm CMOS

This programmable engine is designed to offload TCP inbound processing at wire speed for 10-Gb/s Ethernet, supporting 64-byte minimum packet size. This prototype chip employs a high-speed core and a specialized instruction set. It includes hardware support for dynamically reordering out-of-order packets. In a 90-nm CMOS process, the 8-mm/sup 2/ experimental chip has 460 K transistors. First silicon has been validated to be fully functional and achieves 9.64-Gb/s packet processing performance at 1.72 V and consumes 6.39 W.

A 25 GHz 32 b integer-execution core in 130 nm dual-V/sub T/ CMOS

A 32 b integer execution core implements 12 instructions. Circuit and body bias techniques together increase the core clock frequency to 5 GHz. In a 130 nm six-metal dual-V/sub T/ CMOS process, the 2.3 mm/sup 2/ prototype contains 160 k transistors, with RF-ALU units dissipating 515 mW at 1.6 V.

A 28.5 GB/s CMOS non-blocking router for terabit/s connectivity between multiple processors and peripheral I/O nodes

A 28.5 GB/s data router enables a terabits/s bandwidth network. The 6.6M transistor 0.18 /spl mu/m 1.3 V 15 W CMOS LSI has three clocking domains that synchronize data through four 1.06 GB/s links, a B-port crossbar, and five point-to-point links of 4.75 GB/s data throughput each. Test data rates are up to 6.4 Gb/s per wire.

A 10Mbit, 15GBytes/sec bandwidth 1T DRAM chip with planar MOS storage capacitor in an unmodified 150nm logic process for high-density on-chip memory applications

A 10Mb planar 1T-IC DRAM chip is implemented in an unmodified 150nm micro-processor logic process. It achieves 15GBytes/sec bandwidth, 9.5nsec read access time with 197mW power at 1.5V, 110/spl deg/C. Worst-case refresh period is 100/spl mu/S at 110/spl deg/C with refresh power density of 0.18W/cm/sup 2/. Effective bit density of 42Mb/cm/sup 2/ is /spl sim/3/spl times/ better than the best 6T SRAM cache in the same technology.

A 233MHz, 80-87% efficient, integrated, 4-phase DC-DC converter in 90nm CMOS

We demonstrate an integrated buck DC-DC converter implemented in a 90nm CMOS technology for multi-Vcc microprocessors. High switching frequency (100-317MHz), 4-phase topology, and fast hysteretic control reduce inductor and capacitor sizes by 1000x, thereby enabling off-chip inductors with no magnetic core and an on-chip decoupling capacitor. The converter achieves 80-87.7% efficiency and 10% peak-to-peak output noise.

Bitline leakage compensation (BLC) and leakage reduction (BLR) techniques for 2-3GHz on-chip cache arrays in microprocessors on 90nm logic technology

Bitline leakage compensation (BLC) and leakage reduction (BLR) techniques, implemented for cache arrays on a testchip in a 90nm logic technology, demonstrate improvement in operational frequency from 1.2GHz to 2GHz for BLC, and to 3GHz for BLR, with 17% and 10% area impacts, respectively.