Bradley Bloechel

Area-efficient linear regulator with ultra-fast load regulation

We demonstrate a fully integrated linear regulator for multisupply voltage microprocessors implemented in a 90 nm CMOS technology. Ultra-fast single-stage load regulation achieves a 0.54-ns response time at 94% current efficiency. For a 1.2-V input voltage and 0.9-V output voltage the regulator enables a 90 mV/sub P-P/ output droop for a 100-mA load step with only a small on-chip decoupling capacitor of 0.6 nF. By using a PMOS pull-up transistor in the output stage we achieved a small regulator area of 0.008 mm/sup 2/ and a minimum dropout voltage of 0.2 V for 100 mA of output current. The area for the 0.6-nF MOS capacitor is 0.090 mm/sup 2/.

Dynamic-sleep transistor and body bias for active leakage power control of microprocessors

Sleep transistors and body bias are used to control active leakage for a 32b integer execution core implemented in a 100nm dual V, CMOS technology. A PMOS sleep transistor degrades performance by 4% but offers 20/spl times/ leakage reduction which is further improved with body bias. Time constants for leakage convergence range from 30ns to 300ns allowing 9-44% power savings for idle periods greater than 100 clock cycles.

Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs

Examines the effectiveness of opportunistic use of reverse body bias (RBB) to reduce leakage power during active operation, burn-in, and standby in 0.18 /spl mu/m single-V/sub t/ and 0.13 /spl mu/m dual-V/sub t/ logic process technologies. Investigates its dependencies on channel length, target V/sub t/, temperature and technology generation. Shows that RBB becomes less effective for leakage reduction at shorter channel lengths and lower V/sub t/ at both high and room temperatures, especially when target intrinsic leakage currents are high. RBB effectiveness also diminishes with technology scaling primarily because of worsening short-channel effects (SCE), particularly when target V/sub t/ values are low. A model is given that relates different transistor leakage components to full-chip leakage current, and is validated through test-chip measurements across a range of RBB values.

Forward body bias for microprocessors in 130-nm technology generation and beyond

Device and test chip measurements show that forward body bias (FBB) can be used effectively to improve performance and reduce complexity of a 130nm dual-V/sub T/ technology, reduce leakage power during burn-in and standby, improve circuit delay and robustness, and reduce active power. FBB allows performance advantages of low temperature operation to be realized fully without requiring transistor redesign, and also improves V/sub T/ variations, mismatch, and g/sub m/ /spl times/ r/sub 0/ product.

Scaling trends of cosmic ray induced soft errors in static latches beyond 0.18 /spl mu/

This paper describes an experiment to characterize soft error rate of static latches for neutrons using a neutron beam, with measured soft error rates as a function of diffusion collection areas and supply voltages. The paper also quantifies the effectiveness of two promising hardening techniques and scaling trends.

Measurements and analysis of SER-tolerant latch in a 90-nm dual-V/sub T/ CMOS process

We designed a soft error rate (SER) tolerant latch utilizing local redundancy. We implemented a test chip containing both the standard and SER-tolerant latches in a 90-nm dual-V/sub T/ CMOS process. Accelerated measurements with a neutron beam at Los Alamos National Laboratory demonstrated 10/spl times/ better reliability of the SER-tolerant latch over the standard latch at no speed degradation. The worst case energy and area penalties were 39% and 44%, respectively. Both the energy and area penalties are negligible for standard-latch transistor sizes at least double the minimum width. We analyzed the effects of the recovery time, threshold voltage assignment, and leakage on the SER robustness. The proposed latch can improve reliability of critical sequential logic elements in microprocessors and other circuits.

Neutron soft error rate measurements in a 90-nm CMOS process and scaling trends in SRAM from 0.25-/spl mu/m to 90-nm generation

The neutron soft error rate (SER) dependency on voltage and area was measured for a state-of-the-art 90-nm CMOS technology. The SER increased by 18% for a 10% reduction in voltage, and scaled linearly with diode area. The measured SER per bit of SRAMs in 0.25 /spl mu/m, 0.18 /spl mu/m, 0.13 /spl mu/m, and 90 nm showed an increase of 8% per generation.

A 480-MHz, multi-phase interleaved buck DC-DC converter with hysteretic control

We propose an on-chip 1.8 V-to-0.9 V DC-DC converter aimed to reduce the input current and decoupling requirements of future microprocessors. By utilizing a 90-nm CMOS process, employing a four-phase hysteretic control, and operating at ultra-high frequency of 480-MHz, we achieved a 10% output droop with only 2.5 nF of on-chip decoupling, for 0.5 A of load current. No off-chip decoupling was connected to the output. At 480 MHz the measured efficiency was 72%. At 250 MHz, the efficiency improved to 76% at the cost of a 17% droop or larger decoupling of 11.5 nF. A converter with 100 A rating would require a capacitor of 0.5 /spl mu/F, which is comparable to the size of an on-chip capacitor of a typical microprocessor.

Ultra-low voltage circuits and processor in 180nm to 90nm technologies with a swapped-body biasing technique

A low-voltage swapped-body biasing technique where PMOS bodies are connected to ground and NMOS bodies to Vcc is evaluated. Available measurements show more than 2.6x frequency improvement at 0.5V Vcc and the ability to reduce Vcc by 0.2V for the same frequency compared to no body bias in 180 to 90nm CMOS technologies.

64 GHz and 100 GHz VCOs in 90 nm CMOS using optimum pumping method

A method to optimally pump energy from the transistors to the passive network is presented for the design of integrated 64 GHz and 100 GHz VCOs in 90 nm CMOS. The VCOs use an on-die distributed network, draw /spl sim/25 mA from a 1 V supply and produce oscillations with 0.4 Vp-p amplitudes. Phase noise is <-110 dBc/Hz at 10 MHz offset, and VCO gain is 2 GHz/V.