Peter Sarson

Automotive EEPROM Qualification and Cost Optimization

This paper is about how an EEPROM characterization test program for the automotive market was developed for an initial IP Block, introduced into production and then cost and yield optimized for high volume production without risk to quality or reliability.

Group delay filter measurement using a chirp

To measure a filters group delay in production is never an easy task and to measure the group delay characteristic in quick and timely manner is difficult to say the least. This paper will discuss a simple method that expands on the authors previous works that will demonstrate how to measure the group delay of a filter and how accurately the technique correlates to measurements of the silicon performance made in the lab.

Using Distortion Shaping Technique to Equalize ADC THD Performance Between ATEs

In this paper, we describe how a phase switching technique is used to control the harmonic contents of a generated sinusoidal signal using digital signal processing techniques. We will describe how this technique equalizes the harmonic performance of arbitrary waveform generators installed in a large scale integration test system, allowing extended performance testing of the total harmonic distortion of an analog-to-digital converter that ordinarily would be possible only using more advanced test equipment. Once a device has been characterized and correlated to the bench, a test engineer is required to release the product into production. One of the major issues surrounding this exercise is the difference in the obtained results between testers of the same manufacture for parameters sensitive to harmonics, noise, and spurious components such as total harmonic distortion. By using the techniques developed in this paper, the user will be able to deploy an academic solution to an industrial problem and extend the range of test equipment that ordinarily would need to be discarded for such test requirements. We will then show the gauge repeatability and reproducibility between two testers of the same manufacture, and how using the described technique produces a better correlation, thus allowing less stringent guard-bands to guarantee the performance of those devices that have performance criteria close to the device specification. This work also goes some way to proving previous papers’ works on distortion shaping testing to enhance the spectral performance of arbitrary waveform generators.

A technique for dynamic range improvement of intermodulation distortion products for an Interpolating DAC-based Arbitrary Waveform Generator using a phase switching algorithm

This paper describes a phase switching algorithm for Interpolating Digital-to-Analog Converter (DAC) based Arbitrary Waveform Generators (AWG). This was possible by using the standard phase switching algorithm with the addition of simple phase offset and systematic phase difference adjustment; this was discovered by experimenting with suppression of the intermodulation distortion (IMD) components of a two-tone signal. In this case, we examine the 3rd, 5th and 7th order IMD tones and the effect of the phase switching algorithm and phase shift has on the AWG by measurement with a digitizer. Then we show what the effect of the developed two-tone phase switching technique has upon the performance measurement of a 16-bit Analog-to-Digital Converter (ADC). It is shown that using the original algorithm, no improvement could be achieved for the odd order IMD products. However, by using an even order suppression technique (another phase difference) with a phase shift, a suppression was achieved compared to the standard two-tone signal generation (without phase switching). We show how this technique allows the use of a low-cost tester resource to test IMD products with a higher dynamic range than was previously possible.

Fast Bit Screening of Automotive Grade EEPROMs—Continuous Improvement Exercise

This paper presents the optimization of an existing electrically eraseable programmable read-only memory (EEPROM) production test flow by means of thorough analysis of the faulty dice and the test flow, which leads to an increase in the yield, a significant decrease in test time, and a decrease in the dppm (increase in quality) level leaving the factory. In order to manufacture high quality and cost-effective EEPROMs suitable for automotive underhood applications, several topics must be taken into account. In addition to a high reliability EEPROM technology, the choice of an advanced memory architecture including error correction code and a highly sophisticated screening methodology in production test is necessary to achieve high quality in the field. The EEPROM production test flow must not only be able to screen out weaknesses in the process but must also be cost efficient. A majority of the tests executed in the EEPROM test flow are needed to check the quality of the processed oxides, which are the basic elements to realize the EEPROM function of the memory. Most of these tests are complex and time-consuming.

Yield improvement of an EEPROM for automotive applications while maintaining high reliability

In order to manufacture high quality and cost effective EEPROMs suitable for automotive under-hood applications several topics must be taken into account. As well as a high reliability EEPROM technology the choice of an advanced memory architecture including ECC and a highly sophisticated screening methodology in production test is necessary to achieve high quality in the field. The EEPROM production testflow must not only be able to screen out weaknesses of the process but must also be cost efficient. A majority of the tests executed in the EEPROM test flow are needed to check the quality of the processed oxides which are the basic elements to realize the EEPROM function of the memory. Most of these tests are complex and time consuming. This work will present an optimization of an existing EEPROM production testflow by means of thorough analysis of the faulty dice and the testflow leading to an increase of the yield without reducing quality.

Test time efficient group delay filter characterization technique using a discrete chirped excitation signal

To measure a filters group delay in production is never an easy task and to measure the group delay characteristic in quick and timely manner is difficult to say the least. This paper will discuss a simple method that expands on the authors previous works that will demonstrate how to measure the group delay of a filter and how accurately the technique correlates to measurements of the silicon performance made in the lab. The test time saving and stability of results will be shown as well as the advantages of the technique with regard to having full characterization data available in a production program. Finally it will be shown how the work can be further developed to a potentially more efficient technique.

Measuring Group Delay of Frequency Downconverter Devices Using a Chirped RF Modulated Signal

This paper discusses the implementation possibilities for making Group Delay measurements of RF frequency converting devices using a standard RF semiconductor Automatic Test Equipment (ATE) that cannot be done using the standard S-parameter measurement due to the difference in frequency from the input to the output of the device. We discuss how using a chirp waveform modulating an RF generator can be used to sweep the frequency response of a RF frequency-converting device and how to produce such a modulation waveform in digital signal processing. We will describe how to implement a group delay test based on our previous work in the baseband domain and how to understand the errors pertaining to measuring a Radio Frequency Receiver. The measurement of the Group Delay of an RF front-end filter and post down convert IF filter will be demonstrated. We will also describe how to produce and maintain a stable frequency reference so that any down converted signal would be a true representation of the modulation signal applied to the RF Source and not corrupted by Phase Noise. We will show how to implement a group delay test based on our previous work in the baseband domain and how to understand the errors pertaining to measuring a radio frequency receiver. The measurement of the group delay of an RF mixer and pre and post down convert RF/IF filters will be demonstrated. The central goal of this paper is to demonstrate how a group delay test can be done at RF, with a frequency translating device, in a cheap and effective manner on semiconductor Automatic Test Equipment in a production environment.

A Distortion Shaping Technique to Equalize Intermodulation Distortion Performance of Interpolating Arbitrary Waveform Generators in Automated Test Equipment

This paper demonstrates a phase switching algorithm for Interpolating Digital-to-Analog Converter (DAC) based Arbitrary Waveform Generator (AWG) that resides in Automated Test Equipment (ATE) to test semiconductor devices. This confirms a previous exercise that was made by experiment with different Intermodulation Distortion (IMD) suppression techniques and starting phase shifts to suppress IMD tones of the AWG with the interpolating DAC. We show that the poor performance of the AWG can be improved by using the phase switching algorithm over the installed base of a company’s tester platform. It is also shown that the IMD performance of AWGs across a company’s tester installed base can be equalized, and how it can be achieved using the phase switching technique. We describe how the IMD specifications of the instrument are much worse than those actually measured, and by using phase switching, better performance can be achieved than what would be possible under normal conditions. We present how this technique allows the use of a low-cost tester resource to test IMD products of such as communication application ADCs with a higher dynamic range than what was previously possible.

Fault-based test methodology for analog amplifier circuits

This paper presents a technique for the fault-based test of the analog amplifiers. The circuit defects are modeled with the 2-fault transistor models. The test method combines the amplifier evaluation both in and out of the normal operating region, with the transconductance of the amplifier being the key test parameter. Furthermore, the additional low current test is employed in order to maximize the fault coverage. With all tests performed only at DC, the test time is significantly reduced. The test method is applicable to amplifiers with various structures. The fault-based simulation performed on a typical two-stage operational transconductance amplifier (OTA) exhibits 100% fault coverage.