Friedrich Peter Leisenberger

A Non-Volatile Embedded Memory for High Temperature Automotive and High-Retention Applications

A highly reliable and scalable non-volatile embedded memory cell and technology is described. This embedded technology operates at very low power, and has minimal impact on the analog and digital components used in the SoC design. The main objective of this technology development was to achieve high reliability and high data retention for automotive applications over the extended temperature range from -40deg to 150deg C. A wider range, from -55deg to 180deg C, has been achieved in manufacturing. Full cell, and memory module functionality, and data retention of over 30 years for the automotive temperature range have been achieved. Write cycling of over 200K writes (tested up to 180degC) over the design temperature range has also been achieved. The memory cell and the technology are optimized to operate at very low voltage and consume very low power. The applications requiring high data retention (>50 years), over the industrial or automotive temperature range can be well served with this technology. The data confirms that this technology is a highly manufacturability and a reliable technology for the embedded non-volatile memory applications. The data presented is based on a 0.35mum CMOS technology implementation

Efficient contact screening of compact NVMs for high reliabilty automotive applications

In modern automotive designs double contacts are mandatory to achieve high reliability products and avoid field returns due to contact issues during the lifetime of the product. Using double contacts in compact digital IPs like RAM, ROM or NVMs leads to a dramatic area penalty. High area efficient NMVs are using shared contacts to minimize the area needed to realize the NVM bit cells. Using double contacts would lead to an area increase of approx. 50% of the NVM memory plane. The high quality standard defined for automotive applications can only be fulfilled with a sophisticated contact screening procedure. This work will present a contact screening procedure which is able to detect contacts with a resistivity outside the main contact resistivity distribution. Those outlier have a potential danger to fail during lifetime as shown in this paper.

Evidence of erratic behaviors in p-channel floating gate memories and a cell architectural solution

This work shows for the first time the presence of erratic phenomena in p-channel floating gate memories using Fowler Nordheim tunneling for both program and erase operations. A specific p-channel EEPROM architecture is investigated and found to be intrinsically robust against erratic behaviors. A comparison between the p-channel device and a conventional n-channel Flash is discussed and physical interpretations are suggested.

Fast Bit Screening of Automotive Grade EEPROMs—Continuous Improvement Exercise

This paper presents the optimization of an existing electrically eraseable programmable read-only memory (EEPROM) production test flow by means of thorough analysis of the faulty dice and the test flow, which leads to an increase in the yield, a significant decrease in test time, and a decrease in the dppm (increase in quality) level leaving the factory. In order to manufacture high quality and cost-effective EEPROMs suitable for automotive underhood applications, several topics must be taken into account. In addition to a high reliability EEPROM technology, the choice of an advanced memory architecture including error correction code and a highly sophisticated screening methodology in production test is necessary to achieve high quality in the field. The EEPROM production test flow must not only be able to screen out weaknesses in the process but must also be cost efficient. A majority of the tests executed in the EEPROM test flow are needed to check the quality of the processed oxides, which are the basic elements to realize the EEPROM function of the memory. Most of these tests are complex and time-consuming.

Yield improvement of an EEPROM for automotive applications while maintaining high reliability

In order to manufacture high quality and cost effective EEPROMs suitable for automotive under-hood applications several topics must be taken into account. As well as a high reliability EEPROM technology the choice of an advanced memory architecture including ECC and a highly sophisticated screening methodology in production test is necessary to achieve high quality in the field. The EEPROM production testflow must not only be able to screen out weaknesses of the process but must also be cost efficient. A majority of the tests executed in the EEPROM test flow are needed to check the quality of the processed oxides which are the basic elements to realize the EEPROM function of the memory. Most of these tests are complex and time consuming. This work will present an optimization of an existing EEPROM production testflow by means of thorough analysis of the faulty dice and the testflow leading to an increase of the yield without reducing quality.

Variation and failure characterization through pattern classification of test data from multiple test stages

We describe a framework for characterizing systematic variations and failures through exploring the hidden patterns of test data from multiple test stages. The framework provides prediction of process variations with a fine resolution based on a limited number of probed process parameters. An unsupervised biclustering technique is then utilized to extract grayscale and binary spatial patterns from process parameters and production test results, respectively, through analyzing both item-to-item and die-to-die correlations in subsets of the test data. A template matching technique exploits these spatial patterns to discover connections between process variations and failures detected by production tests. The proposed framework has been verified by an industrial test dataset of a non-volatile memory product. The discovery of comprehensible correlations between process parameters and some production test items was confirmed by the engineers who have insights to the test dataset.