Brian D. Barrick

PROGRAMMABLE DATA PREFETCH PACING

Systems and methods for executing load instructions that avoid order violations

Dual-issuance of microprocessor instructions using dual dependency matrices

Intermediate Register Mapper

Method to maintain order between multiple queues with different ordering requirements in a high frequency system

Allocation of counters from a pool of counters to track mappings of logical registers to physical registers for mapper based instruction executions

Method of updating cache state information where stores only read the cache state information upon entering the queue

Method and systems for executing load instructions that achieve sequential load consistency

PROCESSOR AND METHOD FOR STORE DATA FORWARDING IN A SYSTEM WITH NO MEMORY MODEL RESTRICTIONS

System and method for avoiding deadlocks when performing storage updates in a multi-processor environment