Grit Sommer

A 77 GHz SiGe mixer in an embedded wafer level BGA package

We present a fully operational 77 GHz SiGe mixer assembled in a chip-scale embedded wafer level BGA (eWLB) package. This innovative package has a footprint with a standard pad pitch of 0.5 mm and a standard package height of 0.4 mm. The results demonstrate an excellent potential of the eWLB package concept for mm-wave applications. The measured gain of the packaged mixer is in best case only 1 dB smaller than measured on-wafer. Further, we analyze the transition from the printed circuit board (PCB) to the chip in package. We compare the results of our analysis with the measured performance of the packaged mixers. We achieve a good agreement between simulations and measurements. Finally, we discuss the methods for improving the electrical performance of the packages assembled on the PCB.

A 77-GHz SiGe single-chip four-channel transceiver module with integrated antennas in embedded wafer-level BGA package

We present for the first time a fully operational 77-GHz silicon-germanium (SiGe) single-chip four-channel transceiver module with four integrated antennas assembled in an embedded wafer-level ball grid array (eWLB) package. This eWLB module has a size of 8 mm × 8 mm and a footprint with a standard ball pitch of 0.5 mm. The module includes four half-wave dipole antennas that are realized using the thin-film redistribution layer (RDL) of the eWLB. The antennas are connected to the transceiver chip using 100-Ω differential coplanar strip (CPS) lines realized in the RDL. The ground plane on top of the printed circuit board (PCB) is used as a reflector for the integrated antenna. Due to integration of the antenna in the package, all mm-wave signals are restricted to the package and no mm-wave transitions to the PCB are required. Moreover, the position of the reflector on the top metallization of the PCB is of great advantage, as it makes the integrated antenna unconstrained by the actual PCB material. Thus, the module can be assembled on any type of PCB. We show that using four radiating elements, it is possible to realize radar system with basic 2D beamforming capabilities. The presented results demonstrate the importance of coherent chip-package co-design and the excellent potential of the eWLB for mm-wave system-in-package (SiP) applications.

Multimode TRL Calibration Technique for Characterization of Differential Devices

In this paper, a new comprehensive analytical derivation and discussion of the multimode thru-relfect-line (TRL) calibration based on the new generalized reverse cascade matrices is presented. The advantage of the presented formulation is that it can account for certain symmetries in the measurement setup and reflect them in the symmetry of the derived relationships. The focus is on the two-mode case since this covers the majority of the practical applications. To demonstrate the effectiveness of the new formulation, the practical use of the multimode TRL calibration technique for de-embedding purposes is discussed. The common de-embedding assumptions such as reciprocity and symmetry are analyzed and their consequences on the multimode TRL calibration are discussed. It is shown that these assumptions applied to the embedding networks can reduce the requirements on the reflect standard. The use of the multimode TRL calibration technique for un-terminating purposes is discussed. It is demonstrated that in the special de-embedding case it is possible to completely characterize the partially leaky embedding networks. The problems of interpretation and re-normalization of the measured scattering parameters are also discussed. Finally, the on-wafer measurement results are presented that verify the multimode TRL approach for four-port vector network analyzer calibration and de-embedding of differential devices.

High-

We investigate high-quality (high-Q) inductors implemented in the redistribution layer (RDL) of the fan-in and fan-out area of an embedded wafer-level ball grid array (eWLB) package. The eWLB is an innovative package technology introduced recently for wireless applications. The technology has outstanding capabilities especially for high-frequency and millimeter-wave package design. We demonstrate that inductors realized in the eWLB fan-out area have negligible substrate losses and lower parasitic capacitances compared to inductors in the eWLB fan-in area. As a result, the inductors implemented in the fan-out area offer significantly higher quality factors and higher self-resonance frequencies. We investigate the effects of the chip-to-package interconnection. We show that the chip-to-package transition creates a bottleneck for the integration of high-Q inductors. We demonstrate the advantages of inductors in the fan-out area of the eWLB on the example of a 6-GHz voltage-controlled oscillator (VCO) chip manufactured in a 65-nm complementary metal-oxide-semiconductor process and assembled in an eWLB package. For the LC tank of this example, we use a 1.1-nH high-Q differential fan-out eWLB inductor to reduce the phase noise. For comparison, we investigate a VCO fabricated with a standard on-chip inductor and assembled in the identical eWLB package. Our measurement results demonstrate lower phase noise and higher output power for all VCOs with inductors embedded in the RDL compared to the reference VCO with the on-chip inductor. The measured phase noise for the VCO with the eWLB inductor in the fan-out area is in the best case 9 dB lower than that of the reference VCO with the on-chip inductor. The presented results prove the integration concept and demonstrate the excellent potential of embedded inductors realized in the fan-out area of the eWLB package.

Q

The thru-reflect-line (TRL) is one of the most fundamental and accurate vector network analyzer (VNA) calibration techniques. The multimode TRL calibration method generalizes the standard TRL technique to multimode waveguides. In this paper, the practical use of the multimode TRL calibration technique for de-embedding purposes is discussed. The focus is on the four-port case, since this covers the majority of the practical applications. However, the formulation can be easily extended for networks with higher number of ports. The common de-embedding assumptions such as reciprocity and symmetry are analyzed and their consequences on the multimode TRL algorithm are discussed. It is shown that the reciprocity assumption applied to the embedding networks reduces the requirements on the reflect standard. It is demonstrated that additional assumptions of either identical or symmetrical error networks make it possible to completely resolve the problem related to the reflect standard. Based on the derived formulation, it is shown that the multimode TRL calibration reduces to the traditional TRL de-embedding under reciprocity and symmetry assumptions. The problems of interpretation and re-normalization of the obtained scattering parameters (S-parameters) are also discussed. Finally, the measurement results are presented that verify the multimode TRL approach for de-embedding of four-port differential devices.

Inductors Embedded in the Fan-Out Area of an eWLB

We present a 5.9-to-7.8 GHz voltage-controlled oscillator (VCO) fabricated in a 65 nm CMOS technology and assembled in a chip-scale embedded Wafer Level Ball-Grid-Array (eWLB) package. The VCO uses a high-quality LC-tank inductor, realized in the fan-out area of the package. This inductor achieves a quality factor of 28 at a frequency of 6.5 GHz. Using this high-Q inductor it was possible to reduce the phase noise by as much as 9 dB at a carrier offset of 1 MHz compared to a reference VCO, which is identical to the first one, but uses an integrated on-chip inductor instead. The VCO using the embedded eWLB inductor offers a phase noise of −118.3 dBc/Hz at 1 MHz and achieves an output power of −1.1 dBm. The VCO core consumes 20.2 mA from a 1.2 V supply. The presented results demonstrate an excellent potential for embedded inductors in the fan-out area of an eWLB package for circuits requiring high-Q inductors.

Multimode TRL technique for de-embedding of differential devices

In this paper we analyze the impact of systematic errors in TRL calibration on the extracted equivalent circuit parameters of the measured device. We mainly focus on extraction of RLCG-parameters (resistance, inductance, capacitance, conductance) of transmission lines and inductors. We show how the uncertainties in measured S-parameters and in determined characteristic impedance propagate into RLCG-parameters. In particular, we emphasize the importance and the difficulty of an accurate determination of the imaginary part of characteristic impedance. We use the results of our sensitivity analysis to estimate the accuracy of RLCG-parameter extraction of a coplanar transmission line and a 2.2 nH spiral inductor. Finally, we propose an alternative method for determination of certain RLCG-parameters based on causal relationships.

A 5.9-to-7.8 GHz VCO in 65-nm CMOS using high-Q inductors in an embedded wafer level BGA package

We investigate high-quality (high-Q) inductors realized in the fan-in area and in the fan-out area of the embedded wafer level ball grid array (eWLB) package. We show that the inductors realized in the fan-out area have negligible substrate losses and lower parasitic capacitances compared to the inductors in the fan-in area. As a result, the fan-out inductors offer significantly higher quality factors and higher self-resonance frequencies (SRFs). We also investigate effects of the chip-to-package interconnection. We demonstrate the advantages of fan-out eWLB inductors on the example of a 6 GHz voltage controlled oscillator (VCO) chip manufactured in a 65 nm complementary metal-oxide-semiconductor (CMOS) technology and assembled in an eWLB package. We use a 1.1 nH high-Q differential coupled fan-out eWLB inductor for the LC tank to reduce the phase noise. We use a VCO fabricated with a standard on-chip inductor and assembled in the identical eWLB package as a reference. Measurement results demonstrate lower phase noise and higher output power of all VCOs with embedded eWLB inductors. The measured phase noise for the VCO with the fan-out eWLB inductor is in best case 9 dB lower than that of the reference VCO with the on-chip inductor. The results prove the integration concept and demonstrate excellent potential of inductors realized in the fan-out area of eWLB.

Accurate broadband RLCG-parameter extraction with TRL calibration

In this paper, we present simulation and measurement results of single-ended and differential vertical interconnections realized using the thin-film redistribution layer (RDL) and through encapsulant vias (TEVs) of the embedded wafer level ball grid array (eWLB) package. We demonstrate that the fan-out area of the eWLB can be used advantageous for the design of passive devices using TEV structures. We show simulation and measurement results of inductors and transformers built up by RDL and TEV structures. Thus, these structures are designed in the fan-out volume of the eWLB mold compound. We discuss the electrical performance of the 3D interconnections and embedded passives realized using TEVs. The presented examples demonstrate that the eWLB technology is an attractive candidate for system integration because this technology enables the design of 2D passives in RDL and 3D passives using RDL and TEV.

High-Q embedded inductors in fan-out eWLB for 6 GHz CMOS VCO

In this paper, we introduce a novel technique for vector network analyzer (VNA) scattering parameter (S -parameter) device characterization. The presented approach is based on causal relationships that provide a connection between the real and imaginary parts as well as between the magnitude and phase of causal network functions. We discuss the problems encountered in the practical implementation of the dispersion relationships such as numerical evaluation of the singular integrals, finite bandwidth of the experimental data, reconstruction artifacts, and nonuniqueness of dispersion relationships. To reduce these problems, we use the generalized dispersion relationships with reference points (subtractions). We develop integral relationships with subtractions and corresponding estimates for error bounds. We show that an appropriate placement of the reference points can significantly reduce the errors caused by finite spectrum. We analyze the applicability of the developed dispersion relationships to the VNA measurements. We demonstrate that certain parameters can be measured with considerably higher accuracy compared with other parameters and that it is possible to select samples from the measured data that can be used as reference points for dispersive integrals. Based on these observations, we propose a device characterization technique that consists of the causality-constrained reconstruction of the sensitive parameters of the measured devices based on more accurately measured characteristics. The proposed technique allows one to accurately characterize the parameters, like quality factor of a high-quality (high- Q) inductors or loss tangent of low-loss transmission lines, of which direct measurement is normally not possible due to limited sensitivity and dynamic range of the VNA. To demonstrate the effectiveness of the proposed technique, we reconstruct the resistance and the quality factor of a high-Q inductor from the accurately measured inductance.