Vadim Issakov

A low-power radio chipset in 40nm LP CMOS with beamforming for 60GHz high-data-rate wireless communication

The link budget of multi-Gb/s wireless communication systems around 60GHz improves by beamforming. CMOS realizations for this type of communication are mostly limited to either one-antenna systems [1], or beamforming ICs that do not implement all radio functions [2]. The sliding-IF architecture of [3] uses RF phase shifting, which deteriorates noise performance.

Multimode TRL Calibration Technique for Characterization of Differential Devices

In this paper, a new comprehensive analytical derivation and discussion of the multimode thru-relfect-line (TRL) calibration based on the new generalized reverse cascade matrices is presented. The advantage of the presented formulation is that it can account for certain symmetries in the measurement setup and reflect them in the symmetry of the derived relationships. The focus is on the two-mode case since this covers the majority of the practical applications. To demonstrate the effectiveness of the new formulation, the practical use of the multimode TRL calibration technique for de-embedding purposes is discussed. The common de-embedding assumptions such as reciprocity and symmetry are analyzed and their consequences on the multimode TRL calibration are discussed. It is shown that these assumptions applied to the embedding networks can reduce the requirements on the reflect standard. The use of the multimode TRL calibration technique for un-terminating purposes is discussed. It is demonstrated that in the special de-embedding case it is possible to completely characterize the partially leaky embedding networks. The problems of interpretation and re-normalization of the measured scattering parameters are also discussed. Finally, the on-wafer measurement results are presented that verify the multimode TRL approach for four-port vector network analyzer calibration and de-embedding of differential devices.

High-

We investigate high-quality (high-Q) inductors implemented in the redistribution layer (RDL) of the fan-in and fan-out area of an embedded wafer-level ball grid array (eWLB) package. The eWLB is an innovative package technology introduced recently for wireless applications. The technology has outstanding capabilities especially for high-frequency and millimeter-wave package design. We demonstrate that inductors realized in the eWLB fan-out area have negligible substrate losses and lower parasitic capacitances compared to inductors in the eWLB fan-in area. As a result, the inductors implemented in the fan-out area offer significantly higher quality factors and higher self-resonance frequencies. We investigate the effects of the chip-to-package interconnection. We show that the chip-to-package transition creates a bottleneck for the integration of high-Q inductors. We demonstrate the advantages of inductors in the fan-out area of the eWLB on the example of a 6-GHz voltage-controlled oscillator (VCO) chip manufactured in a 65-nm complementary metal-oxide-semiconductor process and assembled in an eWLB package. For the LC tank of this example, we use a 1.1-nH high-Q differential fan-out eWLB inductor to reduce the phase noise. For comparison, we investigate a VCO fabricated with a standard on-chip inductor and assembled in the identical eWLB package. Our measurement results demonstrate lower phase noise and higher output power for all VCOs with inductors embedded in the RDL compared to the reference VCO with the on-chip inductor. The measured phase noise for the VCO with the eWLB inductor in the fan-out area is in the best case 9 dB lower than that of the reference VCO with the on-chip inductor. The presented results prove the integration concept and demonstrate the excellent potential of embedded inductors realized in the fan-out area of the eWLB package.

Q

The thru-reflect-line (TRL) is one of the most fundamental and accurate vector network analyzer (VNA) calibration techniques. The multimode TRL calibration method generalizes the standard TRL technique to multimode waveguides. In this paper, the practical use of the multimode TRL calibration technique for de-embedding purposes is discussed. The focus is on the four-port case, since this covers the majority of the practical applications. However, the formulation can be easily extended for networks with higher number of ports. The common de-embedding assumptions such as reciprocity and symmetry are analyzed and their consequences on the multimode TRL algorithm are discussed. It is shown that the reciprocity assumption applied to the embedding networks reduces the requirements on the reflect standard. It is demonstrated that additional assumptions of either identical or symmetrical error networks make it possible to completely resolve the problem related to the reflect standard. Based on the derived formulation, it is shown that the multimode TRL calibration reduces to the traditional TRL de-embedding under reciprocity and symmetry assumptions. The problems of interpretation and re-normalization of the obtained scattering parameters (S-parameters) are also discussed. Finally, the measurement results are presented that verify the multimode TRL approach for de-embedding of four-port differential devices.

Inductors Embedded in the Fan-Out Area of an eWLB

As the frequency spectrum below 10GHz is becoming extremely crowded alternative higher frequency bands are getting a large attention despite their associated high dispersion losses and need for a direct line-of-sight. Recently, numerous published work have targeted the free spectrum at 60GHz, but near-future commercial applications may prefer the frequency bands at 17 to 17.2GHz (ETSI) and/or 24 to 24.2GHz (ISM band) to enable the use of cheap package options (VQFN or flip-chip), and classical board- and antenna-mounting techniques.

Multimode TRL technique for de-embedding of differential devices

We present a 5.9-to-7.8 GHz voltage-controlled oscillator (VCO) fabricated in a 65 nm CMOS technology and assembled in a chip-scale embedded Wafer Level Ball-Grid-Array (eWLB) package. The VCO uses a high-quality LC-tank inductor, realized in the fan-out area of the package. This inductor achieves a quality factor of 28 at a frequency of 6.5 GHz. Using this high-Q inductor it was possible to reduce the phase noise by as much as 9 dB at a carrier offset of 1 MHz compared to a reference VCO, which is identical to the first one, but uses an integrated on-chip inductor instead. The VCO using the embedded eWLB inductor offers a phase noise of −118.3 dBc/Hz at 1 MHz and achieves an output power of −1.1 dBm. The VCO core consumes 20.2 mA from a 1.2 V supply. The presented results demonstrate an excellent potential for embedded inductors in the fan-out area of an eWLB package for circuits requiring high-Q inductors.

A 2kV ESD-Protected 18GHz LNA with 4dB NF in 0.13μm CMOS

In this paper we analyze the impact of systematic errors in TRL calibration on the extracted equivalent circuit parameters of the measured device. We mainly focus on extraction of RLCG-parameters (resistance, inductance, capacitance, conductance) of transmission lines and inductors. We show how the uncertainties in measured S-parameters and in determined characteristic impedance propagate into RLCG-parameters. In particular, we emphasize the importance and the difficulty of an accurate determination of the imaginary part of characteristic impedance. We use the results of our sensitivity analysis to estimate the accuracy of RLCG-parameter extraction of a coplanar transmission line and a 2.2 nH spiral inductor. Finally, we propose an alternative method for determination of certain RLCG-parameters based on causal relationships.

A 5.9-to-7.8 GHz VCO in 65-nm CMOS using high-Q inductors in an embedded wafer level BGA package

We investigate high-quality (high-Q) inductors realized in the fan-in area and in the fan-out area of the embedded wafer level ball grid array (eWLB) package. We show that the inductors realized in the fan-out area have negligible substrate losses and lower parasitic capacitances compared to the inductors in the fan-in area. As a result, the fan-out inductors offer significantly higher quality factors and higher self-resonance frequencies (SRFs). We also investigate effects of the chip-to-package interconnection. We demonstrate the advantages of fan-out eWLB inductors on the example of a 6 GHz voltage controlled oscillator (VCO) chip manufactured in a 65 nm complementary metal-oxide-semiconductor (CMOS) technology and assembled in an eWLB package. We use a 1.1 nH high-Q differential coupled fan-out eWLB inductor for the LC tank to reduce the phase noise. We use a VCO fabricated with a standard on-chip inductor and assembled in the identical eWLB package as a reference. Measurement results demonstrate lower phase noise and higher output power of all VCOs with embedded eWLB inductors. The measured phase noise for the VCO with the fan-out eWLB inductor is in best case 9 dB lower than that of the reference VCO with the on-chip inductor. The results prove the integration concept and demonstrate excellent potential of inductors realized in the fan-out area of eWLB.

Accurate broadband RLCG-parameter extraction with TRL calibration

This study compares the key parameters of two integrated receiver front-end architectures: low noise amplifier (LNA) with active mixer against LNA with passive mixer. The authors discuss the differences in the performance and their impact on system characteristics for radar applications. A low-IF down-conversion receiver implementation is considered. The results are compared in measurement for two 24 GHz receiver front-end chips realised in a 0.13 mum digital CMOS process. Both circuits have been characterised over automotive temperature range -40 to 125degC. The front-end with an active mixer offers lower LO power dependence and exhibits better temperature stability, whereas the front-end with a passive mixer has the advantage of better input-referred linearity and lower flicker noise.

High-Q embedded inductors in fan-out eWLB for 6 GHz CMOS VCO

Accurate radiofrequency (RF) characterisation of on-chip or on-board devices often requires de-embedding to account for parallel and serial parasitics associated with bonding pads and interconnects. It is usually performed by well-known techniques such as Open-Short, Pad-Open-Short or Thru. However, these approaches or alternative techniques employing more standards assume a specific lumped-element model of bonding structures. This reduces de-embedding accuracy at higher frequencies. The Thru de-embedding technique is analysed in this paper and it is shown that under certain conditions de-embedding can be performed without modelling of the internal structure of the thru standard. The possibility to obtain the parameters of an error network by using a single test structure reduces significantly the costs of manufacturing standards and saves the measurement time. Further, an extension of the Thru technique is introduced. It is shown that at the expense of one more measurement, it is possible to characterise the system without additional assumptions. The presented method can be applied, for example, for de-embedding of fixtures with different connectors on either side. Additionally, the extension of Thru technique for de-embedding of differential devices is proposed. The paper verifies the extension for asymmetrical structures by simulation performed using Sonnet electromagnetic field solver in the frequency range 1-40-GHz. Finally, the extension for differential devices is verified by measurement in the frequency range 1-20-GHz and comparison of the results with Open-Short de-embedding technique.