Klaus Pressel

Embedded wafer level ball grid array (eWLB) technology for millimeter-wave applications

The embedded wafer level ball grid array (eWLB) is a novel packaging technology that shows excellent performance for millimeter-wave (mm-wave) applications. We present simulation and measurement results of single-ended and differential transmission lines realized using the thin-film redistribution layers (RDL) of an eWLB. We demonstrate the capabilities for the integration of passives on example of a configurable 17/18 GHz down-converter circuit realized in silicon-germanium (SiGe) technology with a fan-in eWLB differential inductor used for the LC tank. We compare the performance of differential chip-package-board transitions realized in an eWLB and in other common package types. We report an optimized compact chip-package-board transition in the eWLB. We obtain a simulated insertion loss as low as −0.65 dB and a return loss below −16 dB at 77 GHz without external matching networks. We introduce the concept of antenna integration in the eWLB and show examples of single-ended and differential antenna structures. Finally, we present for the first time a single-chip four-channel 77 GHz transceiver in SiGe integrated in the eWLB package together with four dipole antennas. The presented examples demonstrate that the eWLB technology is an attractive candidate for mm-wave applications including system-in-package (SiP).

A 77 GHz SiGe mixer in an embedded wafer level BGA package

We present a fully operational 77 GHz SiGe mixer assembled in a chip-scale embedded wafer level BGA (eWLB) package. This innovative package has a footprint with a standard pad pitch of 0.5 mm and a standard package height of 0.4 mm. The results demonstrate an excellent potential of the eWLB package concept for mm-wave applications. The measured gain of the packaged mixer is in best case only 1 dB smaller than measured on-wafer. Further, we analyze the transition from the printed circuit board (PCB) to the chip in package. We compare the results of our analysis with the measured performance of the packaged mixers. We achieve a good agreement between simulations and measurements. Finally, we discuss the methods for improving the electrical performance of the packages assembled on the PCB.

Modern IC packaging trends and their reliability implications

Abstract Reliability aspects are of extreme importance for assembly and packaging, which has become a limiting factor for both cost and performance of electronic systems. On the one hand reliability can be negatively influenced by modern front-end and packaging technology, on the other hand new applications and corresponding field requirements can result in the need for new reliability tests e.g. for mobile devices. Today the three main package trends for mobile devices towards ongoing miniaturization and higher system integration are ball grid array type packages, leadless packages, and wafer level type packages. We present reliability implications based on examples of failures in these modern packaging technologies. We highlight the importance of design for reliability based on results of simulations for a leadless package. For the future it is necessary that test conditions must follow the field requirements to guarantee optimum reliability results.

A 77-GHz SiGe single-chip four-channel transceiver module with integrated antennas in embedded wafer-level BGA package

We present for the first time a fully operational 77-GHz silicon-germanium (SiGe) single-chip four-channel transceiver module with four integrated antennas assembled in an embedded wafer-level ball grid array (eWLB) package. This eWLB module has a size of 8 mm × 8 mm and a footprint with a standard ball pitch of 0.5 mm. The module includes four half-wave dipole antennas that are realized using the thin-film redistribution layer (RDL) of the eWLB. The antennas are connected to the transceiver chip using 100-Ω differential coplanar strip (CPS) lines realized in the RDL. The ground plane on top of the printed circuit board (PCB) is used as a reflector for the integrated antenna. Due to integration of the antenna in the package, all mm-wave signals are restricted to the package and no mm-wave transitions to the PCB are required. Moreover, the position of the reflector on the top metallization of the PCB is of great advantage, as it makes the integrated antenna unconstrained by the actual PCB material. Thus, the module can be assembled on any type of PCB. We show that using four radiating elements, it is possible to realize radar system with basic 2D beamforming capabilities. The presented results demonstrate the importance of coherent chip-package co-design and the excellent potential of the eWLB for mm-wave system-in-package (SiP) applications.

Embedded wafer level ball grid array (eWLB) technology for system integration

Silicon front-end and assembly and packaging technology more and more merge. In addition interconnect density reaches limits for advanced CMOS technology. In this paper we introduce the fan-out embedded wafer level packaging technology, which is an example to link front-end and packaging technology and offers additional freedom for interconnect design. We demonstrate capabilites for system integration of the eWLB technology, which includes system on chip (SoC) integration and system in package (SiP) integration like side by side and stacking of devices. We highlight the importance of understanding properties of new materials, which influence warpage or heat dissipation. We also show the excellent performance of the eWLB package for mm-wave applications.

System integration with eWLB

Fan-Out Wafer Level Packaging has arrived in the industry. The driving factors for the implementation of this packaging technology are the low packaging and test cost, the excellent electrical and thermal performance, the ability to work with increasing interconnect density on chip side and the potential for Integration of functionality. The increasing demand for new and more advanced electronic products with superior functionality and performance is driving the integration of functionality for future packaging technologies.

High-

We investigate high-quality (high-Q) inductors implemented in the redistribution layer (RDL) of the fan-in and fan-out area of an embedded wafer-level ball grid array (eWLB) package. The eWLB is an innovative package technology introduced recently for wireless applications. The technology has outstanding capabilities especially for high-frequency and millimeter-wave package design. We demonstrate that inductors realized in the eWLB fan-out area have negligible substrate losses and lower parasitic capacitances compared to inductors in the eWLB fan-in area. As a result, the inductors implemented in the fan-out area offer significantly higher quality factors and higher self-resonance frequencies. We investigate the effects of the chip-to-package interconnection. We show that the chip-to-package transition creates a bottleneck for the integration of high-Q inductors. We demonstrate the advantages of inductors in the fan-out area of the eWLB on the example of a 6-GHz voltage-controlled oscillator (VCO) chip manufactured in a 65-nm complementary metal-oxide-semiconductor process and assembled in an eWLB package. For the LC tank of this example, we use a 1.1-nH high-Q differential fan-out eWLB inductor to reduce the phase noise. For comparison, we investigate a VCO fabricated with a standard on-chip inductor and assembled in the identical eWLB package. Our measurement results demonstrate lower phase noise and higher output power for all VCOs with inductors embedded in the RDL compared to the reference VCO with the on-chip inductor. The measured phase noise for the VCO with the eWLB inductor in the fan-out area is in the best case 9 dB lower than that of the reference VCO with the on-chip inductor. The presented results prove the integration concept and demonstrate the excellent potential of embedded inductors realized in the fan-out area of the eWLB package.

Q

The embedded wafer level ball grid array (eWLB) is a novel system integration platform introduced recently. The eWLB technology is an attractive solution for high-frequency system-in-package (SiP) integration due to the capability to design high-quality (high-Q) embedded passives in the fan-out region and side-by-side multichip integration possibilities. In this paper, we show examples of using the fan-out region and the thin-film redistribution layer (RDL) advantageous for integration of inductors and antennas into an eWLB package. In addition, the use of the through encapsulant via (TEV) technology can extend the integration capabilities to 3D. We present measurement and simulation results of vertical interconnections realized using the RDL and TEVs of the eWLB. We demonstrate that the fan-out area of the eWLB can be used for the design of passive devices using the combination of TEV and RDL structures. We show examples of 3D inductors and transformers integrated in the eWLB. We present a fully integrated single-chip 60-GHz transceiver integrated in the eWLB package together with two dipole antennas as an example of mm-wave system integration.

Inductors Embedded in the Fan-Out Area of an eWLB

We present a 5.9-to-7.8 GHz voltage-controlled oscillator (VCO) fabricated in a 65 nm CMOS technology and assembled in a chip-scale embedded Wafer Level Ball-Grid-Array (eWLB) package. The VCO uses a high-quality LC-tank inductor, realized in the fan-out area of the package. This inductor achieves a quality factor of 28 at a frequency of 6.5 GHz. Using this high-Q inductor it was possible to reduce the phase noise by as much as 9 dB at a carrier offset of 1 MHz compared to a reference VCO, which is identical to the first one, but uses an integrated on-chip inductor instead. The VCO using the embedded eWLB inductor offers a phase noise of −118.3 dBc/Hz at 1 MHz and achieves an output power of −1.1 dBm. The VCO core consumes 20.2 mA from a 1.2 V supply. The presented results demonstrate an excellent potential for embedded inductors in the fan-out area of an eWLB package for circuits requiring high-Q inductors.

Embedded wafer level ball grid array (eWLB) technology for high-frequency system-in-package applications

We investigate high-quality (high-Q) inductors realized in the fan-in area and in the fan-out area of the embedded wafer level ball grid array (eWLB) package. We show that the inductors realized in the fan-out area have negligible substrate losses and lower parasitic capacitances compared to the inductors in the fan-in area. As a result, the fan-out inductors offer significantly higher quality factors and higher self-resonance frequencies (SRFs). We also investigate effects of the chip-to-package interconnection. We demonstrate the advantages of fan-out eWLB inductors on the example of a 6 GHz voltage controlled oscillator (VCO) chip manufactured in a 65 nm complementary metal-oxide-semiconductor (CMOS) technology and assembled in an eWLB package. We use a 1.1 nH high-Q differential coupled fan-out eWLB inductor for the LC tank to reduce the phase noise. We use a VCO fabricated with a standard on-chip inductor and assembled in the identical eWLB package as a reference. Measurement results demonstrate lower phase noise and higher output power of all VCOs with embedded eWLB inductors. The measured phase noise for the VCO with the fan-out eWLB inductor is in best case 9 dB lower than that of the reference VCO with the on-chip inductor. The results prove the integration concept and demonstrate excellent potential of inductors realized in the fan-out area of eWLB.