Gu Yeon Wei

A Wide-Tracking Range Clock and Data Recovery Circuit

A hybrid analog-digital quarter-rate clock and data recovery circuit (CDR) that achieves a wide-tracking range and excellent frequency and phase tracking resolution is presented in this paper. A split-tuned analog phase-locked loop (PLL) provides eight equally spaced phases needed for quarter-rate data recovery and the digital CDR loop adjusts the phase of the PLL output clocks in a precise manner to facilitate plesiochronous clocking. The CDR employs a second-order digital loop filter and combines delta-sigma modulation with the analog PLL to achieve sub-picosecond phase resolution and better than 2 ppm frequency resolution. A test chip fabricated in a 0.18 mum CMOS process achieves BER <10-12 and consumes 14 mW power while operating at 2 Gb/s. The tracking range is greater than plusmn5000 ppm and plusmn2500 ppm at 10 kHz and 20 kHz modulation frequencies, respectively, making this CDR suitable for systems employing spread-spectrum clocking.

Analysis of PLL clock jitter in high-speed serial links

We analyze the effects of transmitter and receiver phased-locked loop (PLL) phase noise, which translates to time-domain clock/data jitter, on the performance of high-speed transceivers. Analytical expressions are derived to incorporate both transmitter and receiver clock jitter into serial link operation. A method to calculate the worst-case noise margin degradation due to clock jitter is discussed in order to obviate impractical time-domain simulations. This analysis relies on the assumption that the channel is linear and time-invariant and, hence, can be characterized by an impulse response. A simple extension to equalized serial links is also presented. The analysis is verified through behavioral simulations using a realistic/measured channel model.

A Sub-Picosecond Resolution 0.5–1.5 GHz Digital-to-Phase Converter

A digital-to-phase converter (DPC) is an essential building block in applications such as source-synchronous interfaces and digital phase modulators. The resolution of DPCs using analog phase interpolators is severely affected by the operating frequency and rise times of the interpolator inputs. In this paper, we present a new DPC architecture that achieves high resolution independent of both the operating frequency and the rise time. The 8 phases generated by a phase-locked loop are dithered using a delta-sigma modulator to shape the truncation error to high frequency and is subsequently filtered using a delay-locked loop phase filter. The test chip, fabricated in a 0.13 mum CMOS process, operates from 0.5 -1.5 GHz and achieves a differential nonlinearity of less than plusmn0.1 ps and an integral nonlinearity of plusmn12 ps. The total power consumption while operating at 1 GHz is 15 mW.

Digitally-Enhanced Phase-Locking Circuits

In this paper, we present an overview of digital techniques that can overcome the drawbacks of analog phase-looked loops (PLLs) implemented in deep-submicron CMOS processes. The design of key building blocks of digital PLLs such as the time-to-digital converter and digital-to-frequency converters are discussed in detail. The implementation and measured results of two digital PLL architectures, (1) based on a digitally controlled oscillator and (2) based on a digital phase accumulator, are presented. The experimental results demonstrate the feasibility of using digital PLLs in digital systems requiring high-performance PLLs.

An 8

This paper presents the design of an 8 channel, 5 & Gb/s per channel parallel receiver with collaborative timing recovery and no forwarded clock. The receiver architecture exploits synchrony in the transmitted data streams in a parallel interface and combines error information from multiple phase detectors in the receiver to produce one global synthesized clock. This collaborative timing recovery scheme enables wideband jitter tracking without increasing the dithering jitter in the synthesized clock. Circuit design techniques employed to implement this receiver architecture are discussed. Experimental results from a 130 nm CMOS test chip demonstrate the enhanced tracking bandwidth and lower dithering jitter of the recovered clock.

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This paper explores the architecture and design of an 8x3.2 Gb/s parallel receiver that relies on collaborative timing recovery. Given synchrony between parallel data channels, per-channel clock recovery can be replaced by a single global timing-recovery (TR) block to save power. Moreover, collecting timing-error information across all of the data channels greatly enhances effective edge transition density, which decreases dithering jitter on the recovered clock.

5 Gb/s Parallel Receiver With Collaborative Timing Recovery

A digital clock and data recovery circuit employs simple 3-level digital-to-analog converters to interface the digital loop filter to the voltage controlled oscillator and achieves low jitter performance. Test chip fabricated in a 0.13mum CMOS process achieves BER < 10-12 , plusmn1500ppm lock-in range, plusmn2500ppm tracking range, recovered clock jitter of 8.9ps rms and consumes 12mW power from a single-pin 1.2V supply, while operating at 1.6Gbps

An 8×3.2Gb/s Parallel Receiver with Collaborative Timing Recovery

A digital-to-phase converter operating from 0.5-1.5GHz employs oversampling, noise shaping and DLL phase filtering to achieve sub-ps resolution independent of the operating frequency. Test chip fabricated in a 0.13mum CMOS process achieves a DNL below plusmn100fs and plusmn12ps INL and consumes 15mW while operating at 1GHz

A 1.6Gbps Digital Clock and Data Recovery Circuit

This paper describes the design and implementation of a 8times5 Gb/s source-synchronous receiver in a 0.13 mum CMOS technology. The receiver employs a cascaded-DLL architecture that avoids filtering of the jitter on the received clock to enhance jitter tolerance bandwidth. A technique is proposed to correct phase spacing mismatch in DLLs that reduces the error standard deviations by more than 40% and improves receiver timing margins.

A Sub-Picosecond Resolution 0.5-1.5GHz Digital-to-Phase Converter

A hybrid analog and digital quarter-rate clock and data recovery circuit employs a second-order digital loop filter with delta-sigma truncation to achieve sub-ps phase resolution and better than 2ppm frequency resolution. A test chip fabricated in a 0.18mum CMOS process achieves BER < 10-12 and consumes 14mW power while operating at 2Gbps. The tracking range is greater than plusmn5000 ppm and plusmn2500 ppm at 10kHz and 20kHz modulation frequencies respectively, thus, making this CDR suitable for systems with spread spectrum clocking