Volodymyr Kratyuk

A Design Procedure for All-Digital Phase-Locked Loops Based on a Charge-Pump Phase-Locked-Loop Analogy

In this brief, a systematic design procedure for a second-order all-digital phase-locked loop (PLL) is proposed. The design procedure is based on the analogy between a type-II second-order analog PLL and an all-digital PLL. The all-digital PLL design inherits the frequency response and stability characteristics of the analog prototype PLL

A Digital PLL With a Stochastic Time-to-Digital Converter

A new dual-loop digital phase-locked loop (DPLL) architecture is presented. It employs a stochastic time-to-digital converter (STDC) and a high-frequency delta-sigma dithering to achieve wide PLL bandwidth and low jitter at the same time. The STDC exploits the stochastic properties of a set of latches to achieve high resolution. A prototype DPLL test chip has been fabricated in a 0.13-mum CMOS process, features a 0.7-1.7-GHz oscillator tuning range and a 6.9-ps rms jitter, and consumes 17 mW under 1.2-V supply while operating at 1.2 GHz.

A Digital PLL with a Stochastic Time-to-Digital Converter

A new dual-loop digital PLL (DPLL) architecture is presented. It employs a stochastic time-to-digital converter (STDC) and a high frequency delta-sigma dithering to achieve a wide PLL bandwidth and low jitter at the same time. The test chip has been fabricated in a 0.13mum CMOS process. The DPLL features a 0.7-1.7 GHz oscillator tuning range, 6.9ps rms jitter and consumes 17mW while operating at 1.2GHz

A Sub-Picosecond Resolution 0.5–1.5 GHz Digital-to-Phase Converter

A digital-to-phase converter (DPC) is an essential building block in applications such as source-synchronous interfaces and digital phase modulators. The resolution of DPCs using analog phase interpolators is severely affected by the operating frequency and rise times of the interpolator inputs. In this paper, we present a new DPC architecture that achieves high resolution independent of both the operating frequency and the rise time. The 8 phases generated by a phase-locked loop are dithered using a delta-sigma modulator to shape the truncation error to high frequency and is subsequently filtered using a delay-locked loop phase filter. The test chip, fabricated in a 0.13 mum CMOS process, operates from 0.5 -1.5 GHz and achieves a differential nonlinearity of less than plusmn0.1 ps and an integral nonlinearity of plusmn12 ps. The total power consumption while operating at 1 GHz is 15 mW.

A Sub-Picosecond Resolution 0.5-1.5GHz Digital-to-Phase Converter

A digital-to-phase converter operating from 0.5-1.5GHz employs oversampling, noise shaping and DLL phase filtering to achieve sub-ps resolution independent of the operating frequency. Test chip fabricated in a 0.13mum CMOS process achieves a DNL below plusmn100fs and plusmn12ps INL and consumes 15mW while operating at 1GHz

Analysis of supply and ground noise sensitivity in ring and LC oscillators

Supply and ground noise sensitivity of a wide variety of ring and LC oscillators has been analyzed based on the perturbation projection vector (PPV) technique. The resulting PPV provides an understanding of how specific frequency content of supply/ground noise is converted to oscillator phase noise. Based on this analysis oscillators that are tolerant of supply/ground noise can be identified and used for low noise oscillator design.

A 0.6GHz to 2GHz Digital PLL with Wide Tracking Range

A digital PLL employing an adaptive tracking technique and a novel frequency acquisition scheme achieves a wide tracking range and fast frequency acquisition. The test chip fabricated in a 0.13 mum CMOS process operates from 0.6 GHz to 2 GHz and achieves better than plusmn3200 ppm frequency tracking range when the reference clock is modulated with a 1 MHz sine wave.

Accurate Simulation of RF MEMS VCO performance including phase noise

A new coupled circuit and electrostatic/mechanical simulator (COSMO) is presented for the design of low phase noise radio frequency (RF) microelectromechanical systems (MEMS) voltage-controlled oscillators (VCOs). The numerical solution of device level equations is used to accurately compute the capacitance of a MEMS capacitor. This coupled with a circuit simulator facilitates the simulation of circuits incorporating MEMS capacitors. In addition, the noise from the MEMS capacitor is combined with a nonlinear circuit-level noise analysis to determine the phase noise of RF MEMS VCO. Simulations of two different MEMS VCO architectures show good agreement with experimentally observed behavior.

A low spur fractional-N frequency synthesizer architecture

A new architecture of a fractional-N phase-locked loop (PLL) frequency synthesizer is presented in this paper. The unique feature of the proposed frequency synthesizer is a loop filter with a discrete time comb filter which allows for the efficient suppression of fractional spurs. The proposed loop filter architecture can be efficiently implemented using switched capacitor techniques. The benefits of this approach are a low power frequency synthesizer design with low spur levels. An analysis of the fractional spurs in the fractional-N frequency synthesizers is also presented.

An 8mW 10b 50MS/s pipelined ADC using 25dB opamp

In 10-bit 50 MS/s pipelined ADC is presented. A 25 dB open loop dc gain amplifier is employed in the MDAC operation. The low opamp dc gain in the extreme is tolerated due to the use of a reference scaling scheme in conjunction with a background offset calibration. An intermediate gain stage is inserted into the pipeline to compensate for the accumulated reduction of reference and signal swing. The prototype IC implemented in a 90 nm CMOS process achieves -63.2 dB THD, 48.8 dB SNR, and 48.6 dB SNDR, while consuming 8 mW from a 1 V supply.