Ming-Da Tsai

A Fully Integrated 16-Element Phased-Array Transmitter in SiGe BiCMOS for 60-GHz Communications

A fully-integrated 16-element 60-GHz phased-array receiver is implemented in IBM 0.12-μm SiGe BiCMOS technology. The receiver employs RF-path phase-shifting and is designed for multi-Gb/s non-line of sight links in the 60-GHz ISM band (IEEE 802.15.3c and 802.11ad). Each RF front-end includes variable-gain LNAs and phase shifters with each front-end capable of 360° variable phase shift (11.25° phase resolution) from 57 GHz to 66 GHz with coarse/fine gain steps. A detailed analysis of the noise trade-offs in the receiver array design is presented to motivate architectural choices. The hybrid active and passive signal-combining network in the receiver uses a differential cross-coupled Gysel power combiner that reduces combiner loss and area. Each array front-end has 6.8-dB noise figure (at 22°C ) and the array has -10 dB to 58 dB programmable gain from single-input to output. Sixteen 60-GHz aperture-coupled patch-antennas and the RX IC are packaged together in multi-layer organic and LTCC packages. The packaged RX IC is capable of operating in all four IEEE 802.15.3c channels (58.32 to 64.8 GHz). Beam-forming and beam-steering measurements show good performance with 50-ns beam switching time. 5.3-Gb/s OFDM 16-QAM and 4.5 Gb/s SC 16-QAM links are demonstrated using the packaged RX ICs. Both line-of-sight links (~7.8 m spacing) and non-line-of-sight links using reflections (~9 m total path length) have been demonstrated with better than -18 dB EVM. The 16-element receiver consumes 1.8 W and occupies 37.7 mm2 of die area.

A 16-element phased-array receiver IC for 60-GHz communications in SiGe BiCMOS

A 0.12-µm SiGe phased-array Rx IC for beam-steered wireless communication in the 60-GHz band is described. It has 16 RF phase-shifting front-ends with 11° digital phase resolution and hybrid passive-active RF signal combining. It achieves 7.4–7.9 dB NF (not including 12-dB array gain) over the 4 IEEE channels. The IC has a double-conversion superheterodyne Rx core with a maximum of 72 dB of power gain in 1-dB steps, and the on-chip synthesizer achieves ≪ −90 dBc/Hz Rx phase noise at 1MHz offset. The IC draws 1.8 W at 2.7 V with a die area of 38 mm2. It has been packaged with 16 antennas in a 288-pin organic BGA and phased-array beamsteering has been demonstrated, along with 5+ Gb/s wireless links using 16-QAM OFDM.

Single-element and phased-array transceiver chipsets for 60-ghz Gb/s communications

This article summarizes the development of mature and highly integrated SiGe BiCMOS ICs for gigabit-per-second communications according to the requirements of the IEEE 802.15.3c and 802.11.ad-draft standards. A single-element transceiver chipset for point-to-point communications is described with emphasis on a feature-rich yet compact 60-GHz receiver. Next, a 16-element phased-array transceiver chipset for non-line-of-sight communications is described, with emphasis on a new power-efficient phased-array transmitter. Examples of gigabit-per-second line-of-sight and non-line-of-sight link experiments are provided, and system-level implementation trade-offs are discussed.

60GHz passive and active RF-path phase shifters in silicon

Integrated 60-GHz active and passive phase shifters for RF-path phase-shifting phased array transceivers are demonstrated in this paper. The reflection-type passive phase shifter achieves ≫180° phase variation across the 57GHz–64GHz band with insertion loss varying from 4.2dB–7.5dB at 60GHz. The active phase shifter employs vector-interpolation architecture and achieves 360° phase variation, −2dB gain, 12GHz 3dB bandwidth and 16.5dB noise figure at 60GHz. Measurements over process and temperature are also discussed and comparisons are drawn between active and passive phase shifting approach for 60GHz phased arrays.

A 0.13

This paper presents a single-chip CMOS quad-band (850/900/1800/1900 MHz) RF transceiver for GSM/GPRS/EDGE applications which adopts a direct-conversion receiver, a direct-conversion transmitter and a fractional-N frequency synthesizer with a built-in DCXO. In the GSM mode, the transmitter delivers 4 dBm of output power with 1deg RMS phase error and the measured phase noise is -164.5 dBc/Hz at 20 MHz offset from a 914.8 MHz carrier. In the EDGE mode, the TX RMS EVM is 2.4% with a 0.5 dB gain step for the overall 36 dB dynamic range. The RX NF and IIP3 are 2.7 dB/-12 dBm for the low bands (850/900 MHz) and 3 dB/-11 dBm for the high bands (1800/1900 MHz). This transceiver is implemented in 0.13 mum CMOS technology and occupies 10.5 mm2. The device consumes 118 mA and 84 mA in TX and RX modes from 2.8 V, respectively and is housed in a 5 times 5 mm2 40-pin QFN package.

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This paper presents an integrated 26-MHz digitally-controlled crystal oscillator (DCXO) with temperature compensation function for multi-standard cellular applications, that achieves a phase noise of -154 and -159 dBc/Hz at 10 kHz and 100 kHz offset, respectively. The frequency instability over temperature is compensated by built-in temperature sensor and compensating capacitor. The frequency instability from -10 to 55 degC is about +/- 1 ppm. The AFC frequency tuning is done by a digitally-controlled metal-oxide-metal capacitor array that is 13-bit thermometer decoded. The DCXO is implemented in a 0.13-mum CMOS technology.

m CMOS Quad-Band GSM/GPRS/EDGE RF Transceiver Using a Low-Noise Fractional-N Frequency Synthesizer and Direct-Conversion Architecture

A four-stage 60 GHz low-noise amplifier is implemented in 65 nm CMOS with nMOS ft of 210 GHz. The LNA incorporates a reflection-type attenuator to provide variable gain with improved linearity in low-gain mode and a tunable notch filter for image rejection. The LNA, which consists of two common-source stages followed by two cascode stages, consumes 30.8 mW and achieves 5.9 dB NF and 15 dB gain at 60 GHz. The variable attenuator provides 10 dB of gain variation with the input-referred 1 dB compression point of the LNA being -15.1 dBm in high gain mode and -6 dBm in the low-gain mode. Each tunable notch filter stage provides an additional 8 dB attenuation of 37 GHz image signals, with the four-stage LNA achieving more than 35 dB image-rejection.

A temperature-compensated low-noise digitally-controlled crystal oscillator for multi-standard applications

The growing demand for high-speed wireless communication has driven the evolution of cellular phone networks. New-generation cellular standards use wider channel bandwidth and more sophisticated modulation to obtain higher data-rates. Due to various cellular standards, chip providers are required to offer highly integrated solutions that support 2G, 3G, and even 4G in one chip. This paper presents a receiver supporting 2G quad bands and 3G TD-SCDMA dual bands. Figure 20.7.1 shows the 2G/3G receiver, whose front-end current-mode outputs are combined at baseband CR filter and biquad PGA, which are shared between all bands. A dynamic gain-bandwidth-product-extension circuit technique is used to remove a transimpedance amplifier to save die area and current.

A 60GHz variable-gain LNA in 65nm CMOS

The RF front-end complexity in 4G multimode multiband cellular radios has increased dramatically, requiring integration of PAs, filters and switches in a single module to reduce the RF footprint. This paper presents a fully integrated multimode TDD transmit front-end module (TXM) supporting GSM/EDGE/TD-SCDMA/TD-LTE in multiple bands. The TXM is implemented with three die on a 2-layer laminate LGA module (Figs. 13.1.1 and 13.1.7). Two multimode multiband power amplifier paths (LB/HB) are implemented in a 0.153µm 1P6M CMOS process, followed by power combiners and harmonic filters in a 0.18µm 3M2V IPD die and finally an SP10T antenna switch in a 0.18µm 1P3M SOI process. The Si substrate of good thermal conductivity dissipates the heat generated by PA transistors to the laminated substrate, which solder mask opened and lots of ground vias are deployed underneath the die to effectively conduct the heat out of the package.

20.7 A multi-band inductor-less SAW-less 2G/3G-TD-SCDMA cellular receiver in 40nm CMOS

This paper presents a 55nm 4-in-1 (11b/g/n, BT, FM, and GPS) radio assembled side-by-side with a 3-metal layer integrated-passive-device (IPD) chip in a QFN40 package. One 2.4GHz transceiver is area-efficiently shared between WiFi and Bluetooth systems. Including a 3dB IPD insertion loss, at chip output (antenna port) the saturated output power of the 11bgn integrated PA is 25dBm; the receiver noise figure is 6dB and 7dB in WiFi and BT modes, respectively. The shared synthesizer locks to within 4ppm target frequency during WiFi/BT channel switching in less than 23 usec. Tracking sensitivity of the GPS receiver and the sensitivity of the FM receiver (including IPD loss) are -162dBm and 2.7dBuVrms, respectively. The IPD chip contains a 2.4GHz WiFi/BT balanced tri-section filter and matching network; a 2.4GHz/1.6GHz diplexer; and a GPS 5th order elliptical filter and its matching network. The radio and IPD die sizes are 3.4mm2 and 3.1mm2, respectively.