Stefan Eichenberger

On hazard-free patterns for fine-delay fault testing

This work proposes an effective method for applying fine-delay fault testing in order to improve defect coverage of especially resistive opens. The method is based on grouping conventional delay-fault patterns into sets of almost equal-length paths. This narrows the overall path length distribution and allows running the pattern sets at a higher speed, thus enabling the detection of small delay faults. These small delay faults are otherwise undetectable because they are masked by longer paths. A requirement for this method is to have hazard-free paths. To obtain these (almost) hazard-free paths we use a fast and simple postprocessing step that filters out paths with hazards. The experimental data shows the effectiveness and the necessity of this filtering process.

Defect-oriented cell-aware ATPG and fault simulation for industrial cell libraries and designs

Industry is facing increasingly tougher quality requirements for more complex ICs. To meet these quality requirements we need to improve the defect coverage. This paper presents a new methodology to significantly increase the defect coverage of the test patterns generated by ATPG tools. The fault model used during the ATPG is enhanced to directly target layout-based intra-cell faults. In contrast to previous techniques, such as Gate-Exhaustive, N-Detect, or Embedded-Multi-Detect, which either are too complex for real-world designs or merely improve the probability of detecting intra-cell defects, the new approach targets the actual root causes of intra-cell defects. The newly proposed Cell-Aware-methodology has been evaluated for 90nm and 65nm technologies on 1671 library cells and on 10 real industrial designs with up to 50 million faults. The experimental results show an average increase of 1.2% in defect coverage and a reduction of 420ppm in escape rate for a 50mm2 design.

Modeling Power Supply Noise in Delay Testing

Excessive power supply noise during test can cause overkill. This article discusses two models for supply noise in delay testing and their application to test compaction. The proposed noise models avoid complicated power network analysis, making them much faster than existing power noise analysis tools. can cause performance degradation and

Defect-oriented cell-internal testing

Industry is facing very high quality requirements for todays and tomorrows ICs. Especially in the automotive market these quality requirements need to be fulfilled. To achieve this we need to improve currently used test methods and fault models to improve the overall defect coverage. This paper presents two new methodologies to significantly improve this situation. One method will focus on cell-internal Bridges over a wide range of Bridge resistor values and the second method concentrates on library cell-internal high-resistive Open defects. The fault models used during the ATPG are enhanced to directly target the layout-based intra-cell Open and Bridge defects. Both methods have been evaluated on 1500 library cells of a 65nm technology. In addition the wide range of intracell Bridges has been evaluated on 10 real industrial designs with up to 60 million faults. Various results are presented from all 1500 library cells and from the 10 industrial designs as well.

Towards a World Without Test Escapes: The Use of Volume Diagnosis to Improve Test Quality

With test quality being an imperative, this paper presents a methodology on how to apply volume scan diagnosis - known from the field of yield learning - to the domain of test quality learning. Volume diagnosis allows to drastically accelerate the learning cycle. We give guidelines on how to improve test pattern generation strategies and try to answer which defects can be addressed deterministically with adequate fault models versus where probabilistic methods such as N-detect need be applied. The paper is based on a detailed analysis of scan diagnosis data from a production volume of well over one million devices of a 90 nm product.

Memory Testing Under Different Stress Conditions: An Industrial Evaluation

This paper presents the effectiveness of various stress conditions (mainly voltage and frequency) on detecting the resistive shorts and open defects in deep sub-micron embedded memories in an industrial environment. Simulation studies on very-low voltage, high voltage and at-speed testing show the need of the stress conditions for high quality products; i.e., low defect-per-million (DPM) level, which is driving the semiconductor market today. The above test conditions have been validated to screen out bad devices on real silicon (a test-chip) built on CMOS 0.18 /spl mu/m technology. The IFA (inductive fault analysis) based simulation technique leads to an efficient fault coverage and DPM estimator, which helps the customers upfront to make decisions on test algorithm implementations under different stress conditions in order to reduce the number of test escapes.

Gate-Exhaustive and Cell-Aware pattern sets for industrial designs

Industry is facing very high quality requirements for todays and tomorrows ICs. Especially in the automotive market these quality requirements need to be fulfilled. To achieve this, we need to improve currently used test methods and fault models to improve the overall defect coverage. This paper presents achieved results from 1500 CMOS 65nm library cells and from 10 industrial designs applying Gate-Exhaustive and defect oriented Cell-Aware pattern sets.

On a Statistical Fault Diagnosis Approach Enabling Fast Yield Ramp-Up

The ability to achieve and maintain high yield levels is directly dependent on the capability to detect and analyze repetitive failure mechanisms. In this paper, an advanced statistical diagnosis method, using the final wafer test results, is presented. The new method builds on an existing full diagnosis method, and studies the adaptations needed to turn it into an effective and efficient on-line statistical diagnosis approach. The output of the new approach is a (limited) list of suspect locations, which acts as input for further statistical and physical analysis. The experiments performed show the efficiency as well as the limitations of the proposed approach.

Impact of Temperature on Test Quality

The usage of more advanced, less mature processes during manufacturing of semiconductor devices has increased the need for performing unconventional types of testing, like temperature-testing, in order to maintain the same high quality levels. However, performing temperature-testing is costly. This paper proposes a viable low-cost alternative to temperature testing that quantifies the impact of temperature variations on the test quality and also determines optimal test conditions. The test flow proposed is empirically validated on an industrial-standard die. The results obtained show that majority of the defects that were originally detected by temperature-testing are also detected by the proposed test flow, thereby reducing the dependence on temperature testing to achieve zero-defect quality. Details of an interesting defect behavior at cold test conditions is also presented.

Time-dependent Behaviour of Full Open Defects in Interconnect Lines

Full open defects on interconnect lines cause broken wires to become floating. The voltage of a floating line depends on its topological characteristics, namely parasitic capacitances to neighbouring structures, transistor capacitances of the downstream gate(s) and trapped charge. However, in nanometer CMOS technologies gate oxide thickness is reduced below a few tens of A, resulting in the gate tunnelling leakage strongly influencing the behaviour of defective circuits with full open defects. Floating lines cannot be considered electrically isolated anymore and are subjected to transient evolutions until reaching a quiescent state, determined by the technology and the downstream gate(s). The occurrence of full opens as well as the impact of gate tunnelling leakage are expected to increase for future technologies. The transient response of full open defects on interconnect lines is analysed for nanometer technologies based on predictive technology models. A method to estimate the delay of defective circuits is proposed. Experimental evidence of this behaviour is presented for a test chip design of 0.18 mum technology.