Mehdi Baradaran Tahoori

Testing of quantum cellular automata

There has been considerable research on quantum dot cellular automata (QCA) as a new computing scheme in the nanoscale regimes. The basic logic element of this technology is the majority voter. In this paper, a detailed simulation-based characterization of QCA defects and study of their effects at logic level are presented. Testing of these QCA devices at logic level is investigated and compared with conventional CMOS-based designs. Unique testing features of designs based on this technology are presented and interesting properties have been identified. A testing technique is presented; it requires only a constant number of test vectors to achieve 100% fault coverage with respect to the fault list of the original design. A design-for-test scheme is also presented, which results in the generation of a reduced test set at 100% fault coverage.

Reliable on-chip systems in the nano-era: lessons learnt and future trends

Reliability concerns due to technology scaling have been a major focus of researchers and designers for several technology nodes. Therefore, many new techniques for enhancing and optimizing reliability have emerged particularly within the last five to ten years. This perspective paper introduces the most prominent reliability concerns from todays points of view and roughly recapitulates the progress in the community so far. The focus of this paper is on perspective trends from the industrial as well as academic points of view that suggest a way for coping with reliability challenges in upcoming technology nodes.

Balancing Performance and Reliability in the Memory Hierarchy

Cosmic-ray induced soft errors in cache memories are becoming a major threat to the reliability of microprocessor-based systems. In this paper, we present a new method to accurately estimate the reliability of cache memories. We have measured the MTTF (mean-time-to-failure) of unprotected first-level (L1) caches for twenty programs taken from SPEC2000 benchmark suite. Our results show that a 16 KB first-level cache possesses a MTTF of at least 400 years (for a raw error rate of 0.002 FIT/bit.) However, this MTTF is significantly reduced for higher error rates and larger cache sizes. Our results show that for selected programs, a 64 KB first-level cache is more than 10 times as vulnerable to soft errors versus a 16 KB cache memory. Our work also illustrates that the reliability of cache memories is highly application-dependent. Finally, we present three different techniques to reduce the susceptibility of first-level caches to soft errors by two orders of magnitude. Our analysis shows how to achieve a balance between performance and reliability

Characterization, test, and logic synthesis of and-or-inverter (AOI) gate design for QCA implementation

Quantum-dot cellular automata (QCA) offers a new computing paradigm for nanotechnology. The basic logic elements of this technology are the majority voter (MV) and the inverter (INV). However, an experimental evaluation has shown that MV is not efficiently used during technology mapping by existing logic-synthesis tools. In this paper, we propose the design and characterization of a novel complex, yet very small, QCA logic gate: the and-or-inverter (AOI) gate. The paper presents a detailed simulation-based analysis of the AOI gate, as well as the study of QCA defects and their effects at the logic level. The AOI implements a universal logic gate; all elementary gates can be implemented by the AOI gate. Moreover, many two-level logic functions can be directly implemented by a single AOI gate. The AOI gate performs quite favorably, in terms of digital logic synthesis. Unlike MV, this gate is efficiently used by existing logic-synthesis tools. Our experimental data on synthesis of complex designs show that using the AOI gate instead of MV, results in up to 23.9% logic area savings, while improving the overall delay.

Defects and faults in quantum cellular automata at nano scale

There has been considerable research on quantum dot cellular automata (QCA) as a new computing scheme in the nano-scale regimes. The basic logic element of this technology is majority voter. In this paper, a detailed simulation-based characterization of QCA defects and study of their effects at logic-level are presented. Testing of these devices is investigated and compared with conventional CMOS-based designs. Unique testing features of designs based on this technology are presented and interesting properties have been identified.

Soft error rate estimation and mitigation for SRAM-based FPGAs

FPGA-based designs are more susceptible to single-event upsets (SEUs) compared to ASIC designs. Soft error rate (SER) estimation is a crucial step in the design of soft error tolerant schemes to balance reliability, performance, and cost of the system. Previous techniques on FPGA SER estimation are based on time-consuming fault injection and simulation methods.In this paper, we present an analytical approach to estimate the failure rate of designs mapped into FPGAs. Experimental results show that this technique is orders of magnitude faster than fault injection method while is very accurate. We also present a high-reliable low-cost mitigation technique which can significantly improve the availability of FPGA-based designs. This technique is able to tolerate SEUs in both user and configuration bits of mapped designs.

An accurate SER estimation method based on propagation probability [soft error rate]

In this paper, we present an accurate but very fast soft error rate (SER) estimation technique for digital circuits, based on error propagation probability (EPP) computation. Experiments results and comparison of the results with the random simulation technique show that our proposed method is on average within 6% of the random simulation method and four to five orders of magnitude faster.

An analytical approach for soft error rate estimation in digital circuits

Soft errors due to cosmic rays cause reliability problems during lifetime operation of digital systems, which increase exponentially with Moores law. The first step in developing efficient soft error tolerant schemes is to analyze the effect of soft errors at the system level. In this work, we develop a systematic approach for soft error rate estimation. Experiments on benchmark circuits and comparison of the results with random fault injection (previous work) show that our proposed method is on average 95% accurate while 4-5 orders of magnitude faster.

On the defect tolerance of nano-scale two-dimensional crossbars

Defect tolerance is an extremely important aspect in nano-scale electronics as the bottom-up self-assembly fabrication process results in a significantly higher defect density compared to conventional lithography-based processes. Defect tolerance techniques are therefore essential to obtain an acceptable manufacturing yield. In this paper, we investigate defect tolerance properties of a 2D nano-scale crossbar, which is the basic block of various nano architectures which have been recently proposed. Various nano-wire and switch faults are studied and their impact on the routability of a crossbar are investigated. In the presence of defects, it is still possible to utilize a defective crossbar at reduced functionality, i.e. as a smaller defect-free crossbar. Simulation results for different sizes and defect densities are presented. This proposed approach can be utilized by architecture designers to determine the expected size of functional (defect-free) crossbar based on defect density information obtained from the fabrication process.

Soft Error Susceptibility Analysis of SRAM-Based FPGAs in High-Performance Information Systems

Soft errors due to cosmic particles are a growing reliability threat for VLSI systems. The vulnerability of FPGA-based designs to soft errors is higher than ASIC implementations since the majority of chip real estate is dedicated to memory bits, configuration bits, and user bits. Moreover, single event upsets (SEUs) in the configuration bits of SRAM-based FPGAs result in permanent errors in the mapped design. In this paper we analyze the soft error vulnerability of FPGAs used in information systems. Since the reliability requirements of these high performance information subsystems are very stringent, the reliability of the FPGA chips used in the design of such systems plays a critical role in overall system reliability. We present an analytical approach (versus fault injection) for soft error rate estimation in FPGA-based designs. We also validate the projections produced by our analytical model using field error rates obtained from failure data obtained from a large FPGA-based design used in the logical unit module board of a commercial information system. This comparison confirms that the projections obtained from our analytical tool are accurate (there is an 81% overlap in FIT rate range obtained with our analytical modeling framework and the field failure data studied).